➀ Mixel's MIPI IP customer, Hercules Microelectronics, creates innovative MIPI solutions for dual-display foldable devices; ➁ Offloading foldable display tasks to an external dual display controller to save power and reduce complexity; ➂ Hercules Microelectronics’ HME-H3 FPGA, integrated with Mixel’s MIPI IP, provides a low-power solution for dual-display devices.
Recent #Chiplet news in the semiconductor industry
➀ Researchers from Queen Mary University of London have developed new nanocomposite films from starch, offering a sustainable alternative to petroleum-based materials; ➁ The films are made from abundant natural polymer starch and highly conductive MXene, with potential applications in electronics and sensing; ➂ The nanocomposites can be tailored for various uses, including wearable technology and healthcare, and are biodegradable.
➀ The Nuclear Safety and Environmental Engineering Technology Institute at the China National Nuclear Corporation (CNNC) has achieved a significant milestone by successfully mass-producing a new chip. ➁ This breakthrough represents a major advancement in China's semiconductor industry. ➂ The new chip is set to enhance the nation's technological capabilities and competitiveness in the global market.
➀ The article discusses the use of laser-based alignment for 3D semiconductor chip manufacturing, achieving precision down to fractions of a nanometer. ➁ Traditional methods using microscopes are limited due to the gap between chip layers, whereas the laser-based method overcomes this by using concentric metalenses to project holograms. ➂ The technology could also benefit advanced displacement sensors and startups in the semiconductor field.
➀ Qualcomm's dispute with Arm Holdings is highlighted; ➁ Arm's architectural license agreement with Qualcomm is terminated; ➂ The dispute reflects the challenges posed by tech giants' custom silicon designs to Arm.
➀ Alchip has taped out a 2nm test chip; ➁ The company expects results by the first quarter of next year; ➂ Alchip is working with customers on high-performance 2nm ASIC development.
➀ Sarcina Technology addresses the cost and complexity of 2.5D package design with Bump Pitch Transformers; ➁ BPT replaces expensive silicon TSV interposers with cost-effective RDLs; ➂ Sarcina's BPT aims to democratize 2.5D design for various applications like HPC and AI.
➀ Google is rumored to switch to TSMC's N3E process for Tensor G5; ➁ The report also clarifies that Google has chosen not to use 2nm technology for Tensor G6; ➂ The move could impact the competition in the AI and smartphone chip markets.
➀ The increasing complexity of chip design necessitates efficient debugging solutions for successful prototype verification; ➁ Prototyping plays a crucial role in chip verification by enabling real-world scenario testing and early customer demonstrations; ➂ S2C's Prodigy prototyping solution offers a comprehensive debugging platform with tools like real-time control software, design debugging software, Multi-Debug Module, and ProtoBridge co-simulation software.
➀ Analog Bits showcased its on-die sensing IP and power management solutions at TSMC OIP; ➁ The company highlighted its progress in 3nm and 2nm technology nodes; ➂ Collaborations with Arm were discussed, focusing on power management and clocking IPs.
➀ TSMC is the leading player in the semiconductor industry.
➁ Advanced packaging is becoming a key technology path for chip performance improvement.
➂ TSMC is expected to become the largest packaging service provider with the rapid adoption of Chiplet architecture.
➃ TSMC has invested heavily in advanced packaging technology, with capacity set to grow significantly.
➄ TSMC's CoWoS, InFO, and SoIC technologies are driving the company's leadership in advanced packaging.
➅ TSMC is expanding its capacity to meet the increasing demand for advanced packaging.
➆ TSMC is also investing in optical packaging technology to meet the growing bandwidth needs.
➀ Arm is exploring the feasibility of running LLMs on mobile devices; ➁ Arm's optimization techniques for LLMs on mobile; ➂ The importance of practical use cases for LLMs in mobile devices
➀ Arm's Total Design initiative has doubled in size within a year; ➁ Samsung Foundry, ADTechnology, and Rebellions collaborate on a 2nm AI processor; ➂ The AI CPU chiplet platform is designed for AI/ML training, cloud computing, and high-performance computing workloads.
➀ Chiplet technology breaks down components from a single system-on-chip (SoC) into multiple small chips (chiplets) with specific functions, and then interconnects them using advanced packaging technology to form a system-in-package (SiP). Advanced packaging technology enhances Chiplet design and performance in terms of interconnect density, signal transmission optimization, thermal performance improvement, reduction of process dependency, and heterogeneous integration, accelerating chip design and application deployment.
➁ With the continuous improvement of chip performance, Chiplet design requires higher signal transmission speed from the substrate. Traditional substrates struggle to meet this demand, but glass substrates offer faster signal transmission rates, lower dielectric losses, and higher interconnect density, providing faster signal transmission channels for Chiplet chips. Additionally, glass substrates have larger packaging sizes and good mechanical stability, allowing for more chiplets in the same area, facilitating large-scale integration of Chiplets and enabling more complex system-in-package designs to meet the performance requirements of high-performance computing and artificial intelligence.
➂ On October 18th at 19:30, the 11th 'Xing Xing Chiplet and Advanced Packaging Public Lecture' will feature a talk by Ma Xiaobo, President of Hunan YueMo Research Institute, titled 'Glass Substrate Chiplet Advanced Packaging and Multi-Physical Field Simulation'. Ma will discuss the prospects and industry status of Chiplet advanced packaging technology, share the application advantages of glass substrates in advanced packaging, and focus on multi-physical field simulation for glass substrate Chiplet advanced packaging and the application and future development trends of deep learning in advanced packaging simulation.
➀ The research investigates the effects of adding TiC nanoparticles to aluminum alloy 7075, aiming to enhance casting performance and improve fluidity and surface quality; ➁ TiC nanoparticles were introduced in two concentrations, and their impact on fluidity and microstructure was analyzed; ➂ The results showed a significant improvement in fluidity and surface quality, with finer grain sizes and smoother surfaces.
➀ TSMC's 3DBlox framework addresses complexities in 3DIC design; ➁ Innovations in 2024 focus on simplifying 3D design challenges; ➂ TSMC's strategies for managing electrical and physical constraints in 3DIC systems.
➀ Faraday and Kiwimoore announce the mass production of their jointly developed 2.5D packaging platform; ➁ The platform is a result of collaboration between the two companies; ➂ The platform is designed to enhance ASIC design and AI networking interconnect solutions.
➀ CEA-Leti is developing optical interposers using silicon photonics; ➁ The new technology, called Starac, aims to reduce communication delays; ➂ Starac uses an ONoC for high-speed data transmission between chiplets without intermediate hops.
➀ Researchers demonstrate active optical interposers for chiplet connectivity with minimal latency; ➁ CEA-Leti's Starac technology uses silicon photonics for improved performance and reduced latency; ➂ The technology aims to enable direct communication between chiplets, bypassing traditional routing methods.
➀ Researchers are exploring wireless communication at the chip level using terahertz frequencies to overcome the limitations of traditional wired connections. ➁ This approach, which involves Floquet engineering and dual-signaling architecture, promises high-speed and reliable data transfer between chiplets. ➂ The advancement in wireless communication is crucial for more efficient and scalable computing systems.