❶ Samsung slashed its 2nm wafer price to $20,000, undercutting TSMC's $30,000 by 33% to attract clients amid fierce foundry competition.

❷ Despite cutting investments and delaying Texas fab projects, Samsung secured a $16.5B deal with Tesla for AI chip production, boosting its advanced fab capabilities.

❸ TSMC maintains market dominance with 15 major clients for 2nm nodes, including Intel and NVIDIA, leveraging its full-capacity production and premium pricing strategy.

➀ TSMC has secured 15 customers for its 2nm process (N2) with wafer prices at $30,000 each, including 10 dedicated to high-performance computing (HPC);

➁ Apple reserved half of TSMC's 2nm capacity by booking all initial output at the Baoshan fab, while other clients like Nvidia, Intel, and Google will use the Kaohsiung fab;

➂ TSMC’s 2nm production is projected to reach 45-50k wafers per month in Q4 2025, generating $1.8-3 billion in revenue, with plans to expand to 200k wpm by 2028.

➀ MediaTek and TSMC collaborate on a new SoC using 2nm process technology to enhance smartphone performance and energy efficiency;

➁ TSMC's N2P 2nm process offers 18% higher performance, 36% reduced power consumption, and 1.2× logic density improvement;

➂ Targeting smartphones, automotive, and data centers, mass production is expected by late 2026.

➀ The U.S. CHIPS Act aimed to revive leading-edge logic chip manufacturing, driven by both commercial value and geopolitical security concerns over Taiwan's dominance;

➁ Intel, the primary recipient of funding, failed to achieve timely 2nm (18A) process development due to mismanagement and lack of focus, leading to declining margins and lost foundry opportunities;

➂ CHIPS Act funds were misallocated to non-critical projects, resulting in a failure to establish advanced U.S. chipmaking capabilities and exposing systemic mismanagement.

➀ Marvell Technology introduces a 64Gbit/s bi-directional die-to-die interconnect for xPUs on 2nm and 3nm processes;

➁ The interface achieves over 30Tbit/s/mm bandwidth density, exceeding UCIe by 3x, with adaptive power management reducing consumption by up to 75%;

➂ Features include redundant lanes, automatic repair, and a complete stack spanning application bridge, link layers, and physical interconnect.

➀ Marvell showcased advanced memory technologies at Hot Chips 2025, including dense 2nm SRAM with 17x higher bandwidth density than standard IP, leveraging TSMC's 2nm process and optimized Vmins for lower power consumption;

➁ The company introduced custom HBM solutions using die-to-die interfaces to reduce on-chip area and power, collaborating with major HBM suppliers to enhance AI accelerator compatibility;

➂ Marvell also demonstrated high-capacity DDR memory expanders with integrated Arm Neoverse v2 CPUs and hardware security, improving latency and bandwidth for large-scale AI workloads.

➀ TSMC dismissed two current employees and one former employee suspected of colluding to illegally obtain trade secrets related to its 2nm semiconductor manufacturing process;

➁ The company proactively detected unauthorized file access, initiated internal investigations, and filed legal actions under Taiwan’s National Security Act;

➂ Prosecutors approved detention requests, emphasizing the case’s severity as a breach of national core technology security.

➀ Two former TSMC engineers face charges under Taiwan’s National Security Act for attempting to leak 2nm chip technology to rivals, marking the first case under the 2022 law;

➀ The suspects allegedly stole proprietary semiconductor IP linked to national security, triggering an investigation involving Japanese chip toolmaker Tokyo Electron;

➂ TSMC dominates global advanced chip production, producing 90% of cutting-edge chips, while China’s SMIC and Huawei lag at 7nm, intensifying geopolitical tensions over tech sovereignty.

➀ TSMC detected suspicious activities on August 5, 2025, potentially involving leaks of 2nm process trade secrets through routine monitoring systems;

➁ The company initiated internal investigations and legal measures after identifying unauthorized access to proprietary data;

➂ TSMC terminated employees linked to the incident, reinforcing its commitment to intellectual property protection amid advanced semiconductor development.

➀ Samsung's Q2 chip profit plunged 94% YoY to $288 million, with sales of $20 billion, compared to $4.7 billion profit in Q2 2024;

➁ The company secured a $16.5 billion order from Tesla for its Texas fab and anticipates more large foundry orders, with plans to ramp up 2nm process production in H2;

➂ Samsung noted HBM3E oversupply affecting pricing and is sampling HBM4, targeting volume production in 2025.

➀ Rapidus announced it has commenced prototype production of 2nm Gate-All-Around (GAA) transistors at its new IMM-1 fab in Hokkaido, Japan, marking a significant advancement in semiconductor manufacturing;

➁ The facility achieved milestones including EUV tool installation in December 2024 and completed over 200 equipment installations, with volume production targeted for 2027;

➂ The earthquake-resistant design features specialized steel dampers and sliding column structures to ensure operational stability in seismically active regions.

➀ Rapidus initiates 2nm GAA transistor test wafer production with successful electrical characteristics validation;

➁ Pioneers full single-wafer processing for all frontend steps to enhance precision and defect control using AI-driven optimization;

➂ Process Development Kit (PDK) launch scheduled for Q1 2026, supporting client chip design validation at IIM-1 facility.

➀ The semiconductor industry's high costs have consolidated leading-edge logic fabs to three players: TSMC, Samsung, and Intel;

➁ TSMC's conservative 2nm strategy with GAA/BSPD adoption secured majority market share, while Samsung and Intel faced yield failures and customer losses;

➂ Revenue dominance at 2nm positions TSMC to monopolize future generations, leaving rivals' foundry prospects uncertain.

➀ Intel may halt marketing its 18A process to foundry customers, focusing instead on 14A, which could leverage high-NA EUV advantages to compete with TSMC;

➁ TSMC dominates the 2nm foundry market with high yields and significant planned capacity (50k wpm by 2025, 120-130k wpm by 2026), securing major clients like Apple and AMD;

➂ Existing 18A contracts with Microsoft and Amazon will continue, though Intel’s strategic shift aims to prioritize 14A for future competitiveness.

➀ Semiconductor manufacturing equipment industry is projected to grow at a 7% CAGR, reaching 11.1 million wafers per month (wpm) by 2028, driven by a 69% expansion in advanced process capacity (7nm and below) to 1.4 million wpm.

➁ 2nm-and-below capacity is expected to surge from 200k wpm in 2025 to 500k wpm by 2028, with equipment investment skyrocketing 120% CAGR to $43 billion, supporting mass production of 2nm chips by 2026 and 1.4nm by 2028.

➂ AI-driven demand for powerful computing (training, VR/AR, humanoid robots) is fueling investments across the semiconductor ecosystem, highlighting the industry's role in tech innovation and chip demand.

➀ Ex-Intel CEO Pat Gelsinger advises Japan's Rapidus to develop unique differentiating technologies beyond production efficiency to compete with TSMC.

➁ Rapidus plans to integrate wafer fabrication and advanced packaging at the same facility for faster cycles, though full automation will not be available immediately from 2027.

➂ The company aims to begin 2nm test production with GAA transistors and establish a chiplets R&D center, utilizing ASML EUV lithography tools for future HBM and 3D packaging.

➀ Sofics announces silicon validation of its IP on TSMC's 2nm technology, achieving exceptional power, performance, and area (PPA) metrics near physical limits;

➁ The IP focuses on built-in robustness for advanced integrated circuits, addressing demanding requirements in next-generation semiconductor designs;

➂ Implementation leverages TSMC's nanosheet transistor architecture, positioning the technology for cutting-edge applications.

➀ TSMC's 2nm process yield surpasses 60%, meeting HVM requirements for stable production;

➁ Samsung's 2nm yield lags at 40%, prompting major clients like AMD, Nvidia, and Apple to prioritize TSMC capacity;

➂ TSMC's 2nm wafer price approaches $30,000, with future 1.4nm costs projected to reach $45,000 by 2028.

➀ Imec and Tokyo Electron (TEL) have extended their partnership to advance semiconductor R&D for nodes beyond 2nm, focusing on patterning, logic devices, memory, and 3D integration;

➁ Their prior collaboration achieved breakthroughs in High NA EUV lithography and EUV resist coating technology, critical for production-level EUV adoption;

➂ The renewed efforts target High NA patterning, CFET devices, and sustainable manufacturing processes to drive innovation and reinforce global semiconductor leadership.

➀ TSMC's A16 (1.6nm) wafer prices may surge to $45,000, marking a 50% increase over N2 (2nm) nodes;

➁ Backside Power Delivery Network (BSPDN) technology drives higher costs, benefiting AI/HPC chips but requiring complex manufacturing steps;

➂ Chip development costs for N2 nodes could reach $725 million, limiting adoption to major players like Apple, NVIDIA, and Qualcomm.