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October 24
- IPLM Today and Tomorrow from Perforce
➀ Perforce IPLM centralizes semiconductor IP management, replacing fragmented methods with unified frameworks and enabling efficient design reuse through metadata tracking.
➁ The platform integrates hardware/software workflows, partners with Siemens for cross-domain synergy, and emphasizes global scalability with compliance controls.
➂ Future enhancements focus on AI-driven design assistance, streamlined CI/CD-EDA tool integration, and intuitive user interfaces to meet evolving industry demands.
October 23
- Better Automatic Generation of Documentation from RTL Code
➀ Historically, chip documentation was manually updated, leading to inconsistencies between specifications and implementation;
➁ AMIQ EDA's Specador uses AI to auto-generate documentation from RTL code, supporting multiple hardware languages and integrating with DVT IDE;
➂ It ensures real-time synchronization between code and documentation, significantly reducing human effort and errors.
October 20
- The AI PC: A New Category Poised to Reignite the PC Market
➀ The AI PC revolution integrates dedicated Neural Processing Units (NPUs) directly into devices, enabling on-device AI capabilities without cloud dependency, mirroring the IBM PC's transformative impact.
➁ Apple leads the AI PC market with its vertically integrated M-series chips and Neural Engine, achieving 35 TOPS performance and standardizing AI across all Macs by 2025, outpacing x86 competitors.
➂ Global AI PC shipments are projected to surge 165% in 2025, driven by corporate demand for productivity tools and consumer adoption of local AI applications, reigniting growth in the stagnant PC industry.
- The Rise, Fall, and Rebirth of In-Circuit Emulation: Real-World Case Studies (Part 2 of 2)
➀ Synopsys speed adapters enable high-fidelity system validation by integrating real hardware with emulation, uncovering critical RTL flaws invisible in virtual models;
➁ Physical layer testing via speed adapters reduced PHY programming/training time from months to weeks, improving PCIe Gen5 and UFS interface compliance;
➂ System Validation Server (SVS) exposed PCIe configuration bugs missed by legacy ICE solutions, preventing costly silicon re-spins.
October 19
- CMOS 2.0 is Advancing Semiconductor Scaling
➀ Imec's CMOS 2.0 leverages wafer-to-wafer hybrid bonding (250nm pitch) and backside power delivery networks (BSPDNs) to enable heterogeneous stacking of logic/memory tiers;
➁ Backside connectivity with 120nm-pitch TDVs and extreme wafer thinning optimizes power distribution, reducing IR drops by 122mV in 2nm mobile SoCs;
➂ System-technology co-optimization (STCO) allows specialized functional layers, offering 22% area savings while boosting performance density beyond traditional Moore’s Law scaling.
- CEO Interview with Dr. Bernie Malouin Founder of JetCool and VP of Flex Liquid Cooling
➀ JetCool's innovative SmartPlate™ technology offers 20%+ cooling efficiency improvements over traditional liquid cooling by targeting silicon hotspots and reducing thermal resistance;
➁ Flex's vertical integration enables global delivery of validated rack systems that reduce power consumption by 10-15% and water usage by 90% while accelerating deployment timelines;
➂ The company addresses future-proofing challenges in AI infrastructure through phased cooling solutions from air-cooled pilots to 1MW liquid-cooled racks with smart monitoring capabilities.
October 12
- Selling the Forges of the Future: U.S. Report Exposes China’s Reliance on Western Chip Tools
➀ A U.S. congressional report reveals China spent $38 billion on Western semiconductor tools in 2024, capturing 39% of global market share despite export controls;
➁ Restricted entities like SMIC and Huawei affiliates received 45% of sales, leveraging node-agnostic equipment gaps to produce 7nm chips for military/AI applications;
➂ Nine policy recommendations include expanding export bans, enhancing tracking, and supporting U.S. toolmakers to counter China’s $100B+ semiconductor self-sufficiency drive.
- SEMICON West AZ- Congress & China- Memory Madness- AI Semiconductor Tsunami
➀ The first SEMICON in Arizona showcased strong industry momentum, with Applied Materials launching critical new tools for advanced packaging and chip manufacturing;
➁ A bipartisan congressional report condemns U.S. semiconductor equipment sales to China, urging stricter 300mm tool restrictions amid national security concerns;
➂ AI-driven memory demand could trigger an unprecedented market cycle, with SK Hynix's 900K wafer/month OpenAI deal signaling explosive growth risks and opportunities.
October 8
- From Prompts to Prompt Engineering to Knowing Ourselves
➀ The article examines challenges non-experts face in prompt engineering, revealing their tendency to use ad hoc methods and over-generalize from limited AI interactions;
➁ Participants in a study struggled with understanding AI's distinct response patterns, preferring human-like instructions over data-driven examples;
➂ The gap between human-AI and human-human communication highlights the need for rethinking interaction strategies to optimize AI usability.
October 7
- GaN Device Design and Optimization with TCAD
➀ Silvaco's webinar detailed GaN HEMT design using TCAD tools to model polarization effects and optimize device performance parameters;
➁ The Victory tool suite enables process simulation, machine learning-driven analytics, and SPICE model generation for vertical/lateral GaN structures;
➂ Applications span power electronics markets with validation from ST Microelectronics and Fraunhofer ISIT through digital twin methodologies.
- How the Father of FinFETs Helped Save Moore’s Law
➀ Moore's Law faced collapse in the early 2000s due to planar transistor limitations, including excessive leakage currents and power inefficiency at sub-90nm nodes;
➁ Dr. Chenming Hu invented the 3D FinFET structure, enabling superior electrostatic control and 37-50% efficiency improvements, allowing transistor scaling to 3nm and beyond;
➂ FinFET adoption by Intel (22nm), TSMC (16nm), and Samsung revived Moore's Law, enabling modern AI/5G/HPC chips with densities exceeding 200 million transistors/mm².
- A Remote Touchscreen-like Control Experience for TVs and More
➀ Smart TVs are evolving with touchless interaction through Ceva's MotionEngine technology;
➁ Ceva-MotionEngine Hex enhances remote controls with 6DoF sensing, low latency, and tremor stabilization;
➂ LG's adoption since 2010 highlights the system's reliability for gesture-based UI in home and commercial applications.
October 6
- Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award
➀ Teradyne荣获2025年台积电开放创新平台（OIP）3DFabric测试领域年度合作伙伴，表彰其在多芯片测试方法和CoWoS先进封装技术上的突破；
➁ 双方合作聚焦于UCIe互连和流式扫描测试技术，显著提升3D IC在AI和云计算场景下的测试效率与良率；
➂ 通过TSMC OIP生态系统强化的协同创新模式，加速了异构集成技术在A16/N2工艺节点的商业化进程。
- Sofics’ ESD Innovations Power AI and Radiation-Hardened Breakthroughs on TSMC Platforms
➀ Sofics collaborates with TSMC to provide advanced ESD protection solutions on nodes from 250nm to 2nm, enabling breakthroughs in AI infrastructure and harsh-environment electronics;
➀ Partnering with Celestial AI, Sofics developed low-parasitic ESD IP for photonic interconnects on TSMC 5nm, addressing AI's 'memory wall' with 50-100Gbps bandwidth and radiation-hardened solutions for space applications;
➂ Sofics' 15-year partnership with Magics Technologies delivers radiation-hardened ESD IP for nuclear fusion and aerospace systems, supporting SEE immunity up to 80MeV·cm²/mg.
October 5
- MIN PULSE WIDTH TIMING CHECK The Silent Timing Trap Lurking In Every Sub-5nm Design
➀ Min Pulse Width (MPW) checks are critical for preventing logic errors and metastability in sub-5nm designs, requiring robust Static Timing Analysis (STA) that accounts for waveform degradation, crosstalk, and process variations.
➁ Duty cycle degradation in clock networks, influenced by RC filtering, asymmetric rise/fall delays, and PVT effects, must be mitigated through precise clock tree synthesis and jitter modeling during timing signoff.
➂ Proactive strategies to fix MPW violations include optimizing clock network integrity, adjusting PLL placement, and implementing early MPW checks during the synthesis phase to avoid costly silicon re-spins.
- CEO Interview with Gary Spittle of Sonical
➀ Sonical's CosmOS platform transforms traditional hearables into intelligent, upgradeable devices, enabling developers to create diverse applications such as immersive audio and health monitoring;
➁ RemoraPro technology achieves ultra-low-latency wireless audio (under 20ms), unlocking gaming, live music performance, and real-time communication use cases;
➂ By building an open ecosystem akin to smartphones' app stores, Sonical aims to partner with industry leaders to redefine hearables as the next-gen personal computing platform.
October 3
- CEO Interview with David Zhi LuoZhang of Bronco AI
➀ Bronco AI develops AI-driven agents for design verification (DV) debugging, automating failure analysis across waveforms, logs, RTL/UVM, and specifications to reduce manual effort for engineers；
➁ The company specifically targets the critical bottleneck of DV debugging in chip development, alleviating overloaded experts and enabling teams to accelerate time-to-market；
➂ Unlike competitors focused on general AI tasks, Bronco prioritizes complex DV debug scenarios, leveraging generative AI to operate at multiple abstraction levels while ensuring on-premise data security.
October 2
- Webinar – The Path to Smaller, Denser, and Faster with CPX, Samtec’s Co-Packaged Copper and Optics
➀ Samtec's CPX (Co-Packaged Copper and Optics) integrates copper and optical interconnects to overcome limitations in high-speed data transmission at 224 Gbps.
➁ Matt Burns will present practical strategies for copper's short-reach superiority (up to 1.5m with CPC) and optical's long-reach scalability (CPO), addressing AI/data center challenges.
➂ Samtec's Si-Fly® HD platform enables hybrid CPX deployment on ultra-dense substrates, exemplified by collaborations with system OEMs and Synopsys.
- Thermal Sensing Headache Finally Over for 2nm and Beyond
➀ Effective thermal management is critical for advanced SoCs at 2nm and below to prevent overheating and ensure performance/reliability, but traditional solutions (analog diodes, ring oscillators) face accuracy and voltage limitations.
➁ ProteanTecs' Local Voltage and Thermal Sensor (LVTS) addresses these challenges with ±1.0°C accuracy using core transistors at low voltages, validated for 5nm, 3nm, and 2nm nodes.
➂ LVTS enables granular monitoring, real-time thermal alerts, and flexible integration, outperforming legacy methods in power consumption, size, and coverage—key for DVFS and GAA-based designs.
October 1
- Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation
➀ Synopsys and TSMC enhance collaboration to develop AI-driven multi-die systems using advanced EDA tools and TSMC's N2P/A16制程 and 3D stacking technologies;
➁ Synopsys' 3DIC Compiler platform enables automated 3D IC design for TSMC's SoIC-X and CoWoS封装技术, achieving multiple customer tape-outs;
➂ Integrated IP solutions (HBM4、UCIe) and photonic engines optimize performance for AI data centers and automotive applications, breaking Moore's Law limitations.
- Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025
➀ Alchip and Ayar Labs collaborate to address AI data bottlenecks with co-packaged optics (CPO), replacing traditional copper I/O for 10x power efficiency gains;
➁ Ayar Labs' TeraPHY optical engines enable 100-200ns latency and over 100 Tbps bandwidth via UCIe-A protocol, while Alchip’s chiplets optimize signal integrity;
➂ The solution enhances AI scalability, reducing deployment costs by 30-50% and enabling exascale real-time inference through composable photonics-driven architectures.
September 30
- AI Everywhere in the Chip Lifecycle: Synopsys at AI Infra Summit 2025
➀ Synopsys demonstrated AI-driven end-to-end solutions for chip development at the AI Infra Summit 2025, addressing energy efficiency, design acceleration, and verification demands.
➁ AI-guided EDA tools reduce chip design time by up to 40% and optimize power consumption via techniques like ML-based synthesis and 3D chiplet integration.
➂ Hardware-assisted verification platforms (ZeBu, HAPS) enable quadrillion-cycle testing for complex datacenter chips, supported by collaborations with NVIDIA, AMD, and cloud providers.
- Neurosymbolic code generation. Innovation in Verification
➀ The paper proposes a neurosymbolic approach (NSG) combining neural networks with symbolic static analysis to improve automated Java code generation, achieving 86% syntax correctness and 40% code similarity without relying on large language models;
➀ Cadence experts highlight how NSG integrates compiler-like symbol tables during training, addressing weaknesses of LLMs in generating semantically valid code;
➁ The method shows promise for semiconductor verification by enforcing strict language rules in EDA tools, outperforming GPT-3 and CodeGPT in code accuracy.
September 29
- Analog Bits Steps into the Spotlight at TSMC OIP
➀ Analog Bits announced new IPs including LDOs, droop detectors, and embedded clock LC PLLs on TSMC's N3P and N2P processes;
➁ The company demonstrated automotive-grade power management solutions and received TSMC's 2025 OIP Partner of the Year Award for the second consecutive year;
➂ Collaborations with Socionext and Cerebras highlighted applications in data centers, AI, and chiplet-based designs.
- Synopsys Collaborates with TSMC to Enable Advanced 2D and 3D Design Solutions
➀ Synopsys certifies Ansys tools for TSMC's N3C/N3P/N2P/A16 processes, enabling precise design validation for AI and HPC applications;
➁ The collaboration introduces AI-driven photonic design flow for TSMC's COUPE™ platform, reducing design cycles by 50%;
➂ Joint development of multiphysics analysis tools enhances thermal and signal integrity in 3DIC systems for 5G/6G infrastructure.
September 28
- Via Multipatterning Regardless of Wavelength as High-NA EUV Lithography Becomes Too Stochastic
➀ High-NA EUV lithography faces significant challenges in 2nm node manufacturing due to photon absorption stochastics and reduced depth of focus, leading to edge roughness and resolution limitations;
➁ Multipatterning becomes mandatory for via connections below 10 nm, requiring up to four masks for source-drain contacts even with advanced lithography tools;
➂ Self-aligned patterning techniques and diagonal grid layouts are critical to minimize mask layers and address center-to-center spacing as small as 40 nm.
- CEO Interview with Jiadi Zhu of CDimension
➀ CDimension, led by MIT-trained CEO Jiadi Zhu, is pioneering next-generation 2D semiconductor materials to overcome silicon's limitations in power consumption and integration.
➁ The company's wafer-scale 2D materials reduce transistor power usage by up to 1,000× compared to silicon while enabling quantum computing breakthroughs through ultra-low-noise insulators that extend qubit coherence.
➂ With over 20 patents and partnerships with leading institutions, CDimension is commercializing materials today while targeting hybrid semiconductor-quantum systems within 2-3 years.
September 26
- CEO Interview with Howard Prakash of TekStart
➀ TekStart transformed from a commercialization partner to a semiconductor/AI-focused venture builder, offering end-to-end support for innovators.
➁ Its business unit Newport by ChipStart delivers 65 TOPS at under 2W, addressing supply chain resilience and AI-driven edge computing demands.
➂ Key applications include security, agriculture, AR/VR, and industrial automation, emphasizing real-time intelligence and energy efficiency.
September 25
- Scaling Debug Wisdom with Bronco AI
➀ AI应用的概念验证需转向可扩展解决方案以实现产品化成功；
➁ 验证（DV）调试的主要挑战是故障分类而非极端案例问题，错误分配导致时间浪费；
➂ Bronco AI通过自动化回归结果分析与任务分配，结合工程师经验构建“思维层”提升调试效率。
- TSMC’s Push for Energy-Efficient AI: Innovations in Logic and Packaging
➀ TSMC addresses AI's growing power demands by advancing logic scaling (N2, A16 nodes) and 3D packaging (3D Fabric, SoIC) to achieve 4.2x efficiency gains from N7 to A14.
➁ Innovations like backside power delivery (A16), Compute-In-Memory (4.5x efficiency gain), and AI-driven design tools (Synopsys DSO.AI) optimize power and performance.
➂ 3D packaging technologies (CoWoS, HBM4) and ecosystem collaborations enable 6.7x energy efficiency improvements, positioning TSMC to support sustainable AI growth.