Recent #EDA news in the semiconductor industry
12/27/2024, 02:00 PM UTC
英特尔共同平台代工厂联盟The Intel Common Platform Foundry Alliance
➀ 英特尔需要填满其晶圆厂以保持竞争力；➁ 台积电通过与日本和欧洲的新合作伙伴关系快速发展；➂ 英特尔可能从建立一个共同的代工厂平台联盟中受益。➀ Intel needs to fill its fabs to remain competitive; ➁ TSMC's rapid expansion with new partnerships; ➂ The potential of a Common Foundry Platform Alliance for Intel.
12/24/2024, 02:03 PM UTC
汤姆的硬件2024圣诞前夕之夜'Twas The Night Before Tom's Christmas 2024
➀ 圣诞老人计划在美国建立一个晶圆厂以获得CHIPS法案资金；➁ 圣诞老人在本地劳动力和资金延误上遇到挑战；➂ 圣诞老人寻求科技公司和UPS工人的帮助以挽救项目；➃ 圣诞老人的晶圆厂资产被科技公司收购，他准备使用Mac Minis和AI PC来分发礼物。➀ Santa Claus plans to build a US-based fab for CHIPS Act money; ➁ Santa encounters challenges with local labor and delays in funding; ➂ Santa seeks help from tech companies and a UPS worker to save the project; ➃ Santa's fab assets are acquired by tech companies, and he prepares to deliver gifts using Mac Minis and AI PCs.
12/24/2024, 02:00 PM UTC
如果我是英特尔CEO，我会怎么做？What would you do if you were the CEO of Intel?
➀ 英特尔在技术宣布中转向更加透明的策略；➁ 英特尔PowerVia与台积电Super Power Rail之间的竞争；➂ 安迪·格鲁夫保持‘适度忧虑’的哲学。➀ Intel's shift to a more transparent strategy in technology announcements; ➁ The competition between Intel's PowerVia and TSMC's Super Power Rail; ➂ Andy Grove's philosophy of maintaining a 'healthy amount of paranoia'.
12/23/2024, 12:56 PM UTC
Arm与高通诉讼的后果The Fall-Out From Arm vs Qualcomm
➀ Arm在与高通的诉讼中未能获得禁止高通使用Nuvia设计的基于Arm的核心的裁决；➁ 陪审团未能就Nuvia是否违反了与Arm的许可条款达成一致，Arm有机会就此问题进行重审；➂ 高通律师出示了一份Arm首席执行官撰写的策略文件，其中提出了Arm自行制造芯片的设想，这可能标志着Arm业务模式的重大转变。➀ Arm在诉讼中未能获得其最想要的结果，即禁止高通在PC芯片组中使用Nuvia设计的基于Arm的核心；➁ 虽然陪审团未能就Nuvia是否违反了与Arm的许可条款达成一致意见，但Arm有机会进行重审；➂ 高通律师出示了一份由Arm首席执行官撰写的策略文件，其中设想Arm建造自己的芯片，这可能是Arm业务模式的一个重大转变。
12/23/2024, 01:02 AM UTC
埃德嗅到欧洲的机会Ed Sniffs Euro-Wonga
➀ 埃德认为欧盟的‘ECS经纪’是一个鼓励英国技 术人才获取欧洲资金的方法；➁ 他已经说服部门为研究人员、发明家、初创企业和中小企业参加这些活动提供预算；➂ 他正在探索斯肯索普量子利用欧洲发展基金的机会。➀ Ed sees the EU's 'ECS Brokerage' as a way to encourage UK techies to access European funds; ➁ He has convinced the Department to allocate a budget for researchers, inventors, startups, and SMEs to attend these events; ➂ He is exploring opportunities for Scunthorpe Quantum to benefit from European development funds.
12/19/2024, 08:39 PM UTC
CXL技术终于在2025年到来CXL is Finally Coming in 2025
➀ 计算表达式链接（CXL）技术预计将在2025年从利基市场转向主流应用；➁ CXL对内存扩展的支持是主要驱动力，现在有各种服务器和内存解决方案可用；➂ CXL 2.0和未来的PCIe/CXL版本将实现更高级的应用，如交换和动态内存分配。➀ Compute Express Link (CXL) technology is expected to move from a niche to mainstream use in 2025; ➁ CXL's support for memory expansion is a significant driver, with various server and memory solutions now available; ➂ CXL 2.0 and future generations of PCIe/CXL will enable more advanced use cases like switching and dynamic memory allocation.
12/18/2024, 09:33 PM UTC
Cadence 推出系统芯片片来重组 SoCCadence Rolls Out System Chiplet to Reorganize the SoC
➀ Cadence 推出了基于 Arm 的新型系统芯片片；➁ 文章深入探讨了这一举措背后的动机；➂ The Briefing 系列文章提供了更多见解。➀ Cadence has introduced a new system chiplet based on Arm; ➁ The article delves into the motivations behind this move; ➂ The Briefing series provides further insights.
12/18/2024, 06:00 PM UTC
重置域交叉（RDC）挑战解析Reset Domain Crossing (RDC) Challenges
➀ 现代集成电路设计中，多时钟和异步复位带来的复杂性使得复位逻辑比早期的单时钟设计更为复杂；➁ 重置域交叉（RDC）工具，如Questa RDC，通过对复位逻辑进行静态验证，识别出诸如毛刺和亚稳态等问题；➂ 西门子的Questa RDC在识别结构化和高级复位树问题方面非常有效，确保在tapeout之前保持逻辑完整性。➀ The complexities of modern IC designs with multiple clocks and asynchronous resets make reset logic more challenging than in early single-clock designs; ➁ Reset Domain Crossing (RDC) tools, like Questa RDC, perform static verification on reset logic to identify issues like glitches and metastability; ➂ Siemens' Questa RDC is effective in identifying structural and advanced reset tree issues, ensuring integrity before tapeout.
12/18/2024, 02:00 PM UTC
机器学习与多物理场在3D设计和HBM中的应用ML and Multiphysics Corral 3D and HBM
➀ 3D设计与HBM在先进半导体系统中至关重要；➁ 大型系统设计需要多 芯片封装；➂ 多物理场和机器学习对于优化性能和可靠性至关重要。➀ 3D design with HBM is critical for advanced semiconductor systems; ➁ Large system designs require multi-chiplet integration; ➂ Multiphysics and ML are essential for optimizing performance and reliability.
12/18/2024, 12:02 PM UTC
高通称其Oryon CPU核心仅使用了1%以下的Arm原始技术——Snapdragon X PC芯片的核心几乎完全定制Qualcomm says its Oryon CPU cores have 1% or less of Arm's original technology — cores in Snapdragon X PC chips are almost entirely custom
➀ 高通Oryon CPU核心使用的Arm技术极低；➁ Oryon核心由Gerard Williams III共同创立的公司Nuvia开发；➂ Arm与高通就Nuvia的架构许可和定制设计存在法律纠纷。➀ Qualcomm's Oryon CPU cores use minimal Arm technology; ➁ Oryon cores are developed by Nuvia, a company co-founded by Gerard Williams III; ➂ Legal dispute between Arm and Qualcomm over Nuvia's architecture licenses and custom designs.
12/17/2024, 02:00 PM UTC
微控制器（MCU）现在正拥抱主流网络互连（NoC）MCUs Are Now Embracing Mainstream NoCs
➀ MCU设计从简单到复杂的转变，需要更复杂的互连技术如NoC；➁ 推动这一变化的因素，包括功耗降低、安全标准支持和多协议支持；➂ 设计的可扩展性重要性以及NoC架构如何支持这一点。➀ The shift in MCU design from simple to complex, requiring more sophisticated interconnects like NoC; ➁ The factors driving this change, including power reduction, safety standards, and support for multiple protocols; ➂ The importance of scalability in design and how NoC architectures can support this.
12/17/2024, 10:09 AM UTC
Cadence任命Moshe Gavrielov加入董事会Cadence Appoints Moshe Gavrielov to Board of Directors
➀ 靖思科技宣布任命Moshe Gavrielov加入其董事会；➁ 此任命将于2025年1月1日起生效；➂ Gavrielov目前担任NXP半导体和台湾半导体制造股份有限公司的董事会成员。➀ Cadence Design Systems announced the appointment of Moshe Gavrielov to its board of directors; ➁ The appointment will be effective from January 1, 2025; ➂ Gavrielov is currently a board member at NXP Semiconductors and Taiwan Semiconductor Manufacturing Company Ltd.
12/16/2024, 12:20 PM UTC
蔡崇信与埃隆·马斯克联手机器人C.C.Wei and Elon Musk hooking up on robots
➀ 蔡崇信与埃隆·马斯克正在合作开发多功能机器人；➁ 马斯克计划于2026年推出名为Optimus的多功能人形机器人；➂ 蔡崇信强调无人机和人工智能在水资源、电力等公用事业领域的应用的重要性。➀ C.C. Wei and Elon Musk are collaborating on multifunctional robots; ➁ Musk plans to launch a multifunctional humanoid robot named Optimus in 2026; ➂ Wei emphasizes the importance of drones and AI applications in utilities such as water and electricity provision.
12/13/2024, 02:15 PM UTC
英国在塑料电子领域的领先地位UK Leads In Plastic Electronics
➀ 英国在塑料电子领域是全球的领导者；➁ 曼德尔森勋爵强调了为行业制定路线图的重要性，以从尖端技术走向大众市场；➂ 斯旺西大学和威尔士印刷与涂覆中心参与开发使用塑料电子的新产品线。➀ The UK has been a global leader in the Plastic Electronics sector; ➁ Lord Mandelson emphasized the importance of a roadmap for the industry to move from cutting-edge to mass market; ➂ Swansea University and the Welsh Centre for Printing and Coating are involved in developing new product lines using plastic electronics.
12/13/2024, 09:18 AM UTC
利用人工智能实现更好的光伏材料Using AI to Achieve Better Photovoltaic Materials
➀ 卡尔鲁厄理工学院的研究人员通过人工智能和高通量合成找到了新的有机分子，以提高钙钛矿太阳能电池的效率。➁ 开发的策略可以应用于其他材料研究领域，如新型电池材料。➂ 该团队使参考太阳能电池的效率提高了2%，达到26.2%。➀ Researchers at KIT have found new organic molecules to improve the efficiency of perovskite solar cells with the help of AI and high-throughput synthesis. ➁ The strategy developed can be applied to other areas of material research, such as new battery materials. ➂ The team achieved a two percent efficiency increase for a reference solar cell, reaching 26.2 percent.
12/13/2024, 04:03 AM UTC
英特尔高管称分拆制造部门是一个“开放问题”Intel executive says spinning off manufacturing unit is an 'open question'
➀ 英特尔联席CEO米歇尔·约翰斯顿·霍尔特豪斯和戴维·津斯纳对于分拆英特尔晶圆代工部门持有不同意见；➁ 英特尔正专注于使其18A工艺技术取得成功；➂ 英特尔已收到多个对其18A技术的提案。➀ Michelle Johnston Holthaus and David Zinsner, co-CEOs of Intel, have differing opinions on spinning off the Intel Foundry division; ➁ Intel is focused on making its 18A process technology successful; ➂ Intel has received several requests for proposals (RFPs) for its 18A technology.
12/12/2024, 02:00 PM UTC
芯片度量公司CEO访谈：Mikko UtriainenCEO Interview: Mikko Utriainen of Chipmetrics
➀ 芯片度量公司是一家专注于高宽比3D芯片（如3D NAND和3D DRAM）测量解决方案的芬兰公司；➁ 公司提供测试芯片以加速研发和工艺控制工作流程；➂ 公司的PillarHall测试芯片能够在高宽比腔体中精确测量薄膜特性。➀ Chipmetrics is a Finnish company specializing in metrology solutions for high aspect ratio 3D chips; ➁ They provide test chips to accelerate R&D and process control workflows; ➂ The company's PillarHall test chips enable precise measurements of film properties in high aspect ratio cavities.
12/12/2024, 02:00 PM UTC
寓言：牛仔CEO的故事Fable: The Cowboy CEO
➀ 这位CEO以他的十加仑帽子和牛仔靴闻名，创立的公司收购了60多家电信公司，市值一度高达1860亿美元。➁ 在一个季度亏损的情况下，公司报告了138亿美元的净利润。➂ 他从公司借款4.08亿美元来弥补保证金调用，最终违约，并在监狱中度过了13年。➀ The CEO, known for his ten gallon hats and cowboy boots, founded a company that acquired over 60 telecoms companies and had a peak market cap of $186 billion. ➁ In one quarter with a loss, the company reported a net profit of $1.38 billion. ➂ He borrowed $408 million from the company to cover margin calls and defaulted on the debt, spending 13 years in jail.
12/12/2024, 12:35 PM UTC
Synopsys发布Ultra Ethernet和UALink IP，为下一代AI数据中心提供动力Synopsys announces Ultra Ethernet and UALink IP to power the next-generation of AI datacenters
➀ 慧荣科技宣布推出Ultra Ethernet和UALink IP，用于下一代AI数据中心；➁ 这些IP支持高速连接和智能多路径；➂ 预计这些技术将于2025年推出。➀ Synopsys announces Ultra Ethernet and UALink IP for next-generation AI datacenters; ➁ The IPs support high-speed connectivity and intelligent multipathing; ➂ The technologies are expected to be launched in 2025.
12/11/2024, 06:00 PM UTC
如何学习形式验证How I learned Formal Verification
➀ 项学讨论了他学习形式验证的历程；➁ 没有结构化课程学习形式验证所面临的挑战；➂ Axiomise形式验证课程在理解并应用形式验证技术方面的好处。➀ Bing Xue discusses his journey into Formal Verification; ➁ Challenges faced in learning FV without structured courses; ➂ Benefits of Axiomise FV courses in understanding and applying FV techniques.
12/11/2024, 10:07 AM UTC
MosChip为C-DAC的HPC处理器“AUM”选择Cadence 5nm EDA工具MosChip selects Cadence tools for the design of HPC Processor “AUM” for C-DAC
➀ 慧荣科技选择Cadence的5nm EDA工具设计C-DAC的HPC处理器“AUM”；➁ 慧荣科技是印度首家公开上市的无厂半导体公司，拥有超过25年设计产品和SoC的经验；➂ 合作旨在利用Cadence的先进工具开发高性能计算解决方案。➀ MosChip selects Cadence's 5nm EDA tools for designing the HPC processor 'AUM' for C-DAC; ➁ MosChip is the first publicly traded fabless semiconductor company in India with over 25 years of experience in designing products and SoCs; ➂ The collaboration aims to leverage Cadence's advanced tools for the development of high-performance computing solutions.
12/11/2024, 08:04 AM UTC
Rapidus与Synopsys推出缩短设计周期的方案Rapidus and Synopsys deliver shortened design cycle
➀ Rapidus与Synopsys合作，采用新方法缩短集成电路设计周期；➁ 该方法旨在减少重新表征的需求，并加速设计迭代；➂ Synopsys将开发先进的设计流程，并在Rapidus的2nm GAA工艺上启用广泛的IP组合。➀ Rapidus and Synopsys collaborate to shorten the IC design cycle with a new approach; ➁ The approach aims to reduce the need for re-characterization and accelerate design iterations; ➂ Synopsys will develop advanced design flows and enable a broad IP portfolio on Rapidus’ 2nm GAA process.
12/10/2024, 06:00 PM UTC
PCB工具中的电气规则检查：HyperLynx DRC解析Electrical Rule Checking in PCB Tools
➀ 介绍PCB设计和验证的挑战；➁ 强调Siemens的HyperLynx DRC的功能特点；➂ 讨论区域裁剪功能及其在PCB设计验证中的优势；➃ 提供MediaTek使用HyperLynx DRC进行复杂PCB设计验证的案例研究。➀ Introduces the challenges in PCB design and verification; ➁ Highlights the features of HyperLynx DRC by Siemens; ➂ Discusses the area-crop function and its benefits in PCB design verification; ➃ Provides a case study of MediaTek using HyperLynx DRC for complex PCB design verification.
12/10/2024, 02:00 PM UTC
Synopsys推出3DIO IP解决方案和3DIC工具，推动多芯片集成Synopsys Brings Multi-Die Integration Closer with its 3DIO IP Solution and 3DIC Tools
➀ Synopsys通过其3DIO IP解决方案和3DIC工具解决多芯片集成挑战；➁ 3DIO IP解决方案包括兼容Synopsys标准单元库的合成友好Tx/Rx单元和高速数据率解决方案；➂ Synopsys的工具能够加快时序收敛并降低多芯片设计中的位错误率。➀ Synopsys addresses the challenges of multi-die integration with its 3DIO IP Solution and 3DIC tools; ➁ The 3DIO IP Solution includes synthesis-friendly Tx/Rx cells and a high data rate solution; ➂ Synopsys' tools enable faster timing closure and reduced bit error rates in multi-die designs.
12/10/2024, 04:44 AM UTC
中国电子集团入主华大九天China Electronics Corporation Takes Control of Huada Jiutian
<p>➀ 中国电子信息产业集团有限公司（中国电子）将成为华大九天的实际控制人。</p><p>➁ 华大九天将被纳入中国电子的合并报表范围。</p><p>➂ 中国电子计划利用其资源和行业联系支持华大九天的发展。</p><p>➀ China Electronics Corporation (China Electronics) will become the actual controller of Huada Jiutian after acquiring a controlling stake.</p><p>➁ Huada Jiutian, a leading domestic EDA company, is set to be integrated into China Electronics' consolidated financial statements.</p><p>➂ China Electronics plans to support Huada Jiutian's development by leveraging its resources and industry connections.</p>
12/09/2024, 03:51 PM UTC
英特尔Arc B580在早期基准测试中与RTX 4060和RX 7600交锋 —— B580在OpenCL和Vulkan工作负载中比A580快30%Intel Arc B580 trades blows with the RTX 4060 and RX 7600 in early benchmarks — B580 beats A580 by up to 30% in OpenCL and Vulkan workloads
➀ 英特尔Arc B580 在早期基准测试中比其前代产品A580快30%以上；➁ 基准测试在OpenCL和Vulkan API上完成；➂ Arc B580的价格低于RTX 4060，但性能快10%。➀ Intel's Arc B580 outperforms its predecessor, A580, by up to 30% in early benchmarks; ➁ The benchmarks were conducted across the OpenCL and Vulkan APIs; ➂ The Arc B580 is 10% faster than the RTX 4060 at a lower price point.
12/09/2024, 06:02 AM UTC
Farnell年终促销Farnell end-of-year sale
➀ 慧荣科技全球宣布在EMEA地区推出测试与工具（T&T）产品的年终促销活动；➁ 该促销活动包括广泛测试与工具产品的显著折扣；➂ 促销活动将于2025年1月31日结束。➀ Farnell Global has announced end-of-year offers on Test & Tools (T&T) products across the EMEA; ➁ The sale includes significant discounts on a wide range of T&T products; ➂ The promotional period ends on January 31, 2025.
12/08/2024, 06:00 AM UTC
香港城市大学发现新型电场信号，具有广泛应用潜力：最新研究成果Observation of New Electric Field Signals Strong Potential for Assorted Devices: New Research at City University of Hong Kong
➀ 香港城市大学的研究人员观察到一种新型涡旋电场，该电场有望提高未来电子、磁性和光学设备的能力；➁ 该研究发表在《科学》杂志上，可能带来内存稳定性和计算速度的改进，并影响量子计算、自旋电子学和纳米技术等领域；➂ 研究团队开发了一种创新的冰辅助转移技术，以创建具有广泛扭转角度的扭曲双层，从而发现了可能提高各种设备功能的二维准晶体。➀ Researchers from City University of Hong Kong have observed a new vortex electric field with potential applications in enhancing future electronic, magnetic, and optical devices; ➁ The research, published in Science, could lead to improved memory stability and computing speed, as well as impact quantum computing, spintronics, and nanotechnology fields; ➂ The team developed an innovative ice-assisted transfer technique to create twisted bilayers with a wide range of twist angles, leading to the discovery of a 2D quasicrystal that may enhance various device capabilities.
12/07/2024, 03:35 PM UTC
博通推出专为AI和HPC设计的巨无霸3.5D XDSiP平台——6000mm²堆叠硅芯片，配备12个HBM模块Broadcom unveils gigantic 3.5D XDSiP platform for AI XPUs — 6000mm² of stacked silicon with 12 HBM modules
➀ 博通推出了专为AI和HPC设计的3.5D XDSiP平台；➁ 该平台采用台积电的CoWoS和其他先进封装技术；➂ 平台支持最多6000mm²的3D堆叠硅芯片和12个HBM模块的系统封装，预计2026年推出。➀ Broadcom unveils its 3.5D XDSiP platform for AI and HPC processors; ➁ The platform utilizes TSMC's CoWoS and advanced packaging technologies; ➂ It allows for SiPs with up to 6000mm² of 3D-stacked silicon and 12 HBM modules, set to arrive in 2026.
12/06/2024, 01:23 PM UTC
被暗杀的联合健康CEO涉嫌使用AI拒绝患病者保险Assassinated UnitedHealthcare CEO allegedly used AI to deny sick people coverage
➀ 一项集体诉讼指控联合健康保险公司使用一个有缺陷的算法拒绝患者保险，由两名现已去世的个人提起。➁ 联合健康保险公司首席执行官布莱恩·汤普森本周在曼哈顿中城被杀，嫌疑 人目前仍在逃。➂ 诉讼声称联合健康保险公司促使员工使用一个错误率约为90%的算法来拒绝保险。➀ A class-action lawsuit alleges that UnitedHealthcare uses a faulty algorithm to deny patient coverage, filed by two now-deceased individuals. ➁ UnitedHealthcare CEO Brain Thompson was killed in Midtown Manhattan earlier this week, and the suspect is currently on the run. ➂ The lawsuit claims UnitedHealthcare pushed employees to use an algorithm with a 90% error rate to deny coverage.
12/05/2024, 06:00 PM UTC
系统就绪认证：确保无缝的Arm处理器部署SystemReady Certified: Ensuring Effortless Out-of-the-Box Arm Processor Deployments
➀ 集成芯片（SoC）设计验证的复杂性，由于硬件和软件之间的交互；➁ 设计缺陷的修复成本随着每个验证阶段的增加而呈指数增长；➂ Arm的系统就绪认证计划通过增强跨设备的软件兼容性和互操作性，简化了验证过程。➀ The complexity of SoC design validation due to hardware-software interactions; ➁ The exponential cost of fixing design bugs increases with each verification stage; ➂ Arm's SystemReady Certification Program simplifies the validation process by enhancing software compatibility and interoperability across devices.
12/05/2024, 08:53 AM UTC
首个可编程连接模块First Programmable Connectivity Module
➀ 本文讨论了首个可编程连接模块，这是电子行业的一项重大发展；➁ 可能探讨了其功能和潜在应用；➂ 该模块可能与连接技术方面的进步有关，影响游戏、人工智能和汽车等各个领域。➀ The article discusses the first programmable connectivity module, a significant development in the electronics industry; ➁ It likely explores its features and potential applications; ➂ The module could be related to advancements in connectivity technology, impacting various sectors such as gaming, AI, and automotive.
12/04/2024, 02:00 PM UTC
与Ansys和Synopsys的大师班：多芯片设计最新进展A Master Class with Ansys and Synopsys, The Latest Advances in Multi-Die Design
➀ 2.5D和3D多芯片设计在主流应用中的兴起；➁ Synopsys和Ansys为多芯片项目提供的全面设计流程；➂ Marc Swinnen和Keith Lanier就技术知识和引人入胜的演示提供的专家见解。➀ The rise of 2.5D and 3D multi-die design in mainstream applications; ➁ Comprehensive design flows provided by Synopsys and Ansys for multi-die projects; ➂ Expert insights from Marc Swinnen and Keith Lanier on technical knowledge and engaging presentation.
12/03/2024, 06:00 PM UTC
SystemC 2024更新：关键进展与未来展望SystemC Update 2024
➀ SystemC进化日聚焦与QEMU的联合仿真；➁ SystemC 3.0.1版本与IEEE标准一致；➂ Fikas促进社区互动；➃ SystemC 1.0庆祝24年发展历程。➀ SystemC Evolution Day focused on co-simulation with QEMU; ➁ SystemC 3.0.1 release aligns with IEEE standards; ➂ Fikas encourage community interaction; ➃ SystemC 1.0 celebrates 24 years of evolution.
12/03/2024, 02:00 PM UTC
Innexis产品套件：推动IC设计和系统开发的左移战略Innexis Product Suite: Driving Shift Left in IC Design and Systems Development
➀ 来自西门子EDA的Innexis产品套件旨在推动IC和系统开发的左移战略；➁ 它提供了工具，用于早期硬件和软件验证，增强了整体开发和验证过程；➂ 套件包括Developer Pro、ANA和VSI等组件，这些组件促进了持续开发和更快的产品上市时间。➀ The Innexis Product Suite from Siemens EDA is designed to enable shift-left methodologies in IC and systems development; ➁ It offers tools for early hardware and software validation, enhancing the overall development and verification process; ➂ The suite includes components like Developer Pro, ANA, and VSI that facilitate continuous development and faster time-to-market.
12/03/2024, 12:00 PM UTC
英特尔面临的困境Intel’s Dilemma
➀ 英特尔在帕特·格尔辛格的领导下初期承诺雄心勃勃，但执行力度不足；➁ 公司面临着臃肿的员工队伍、风险规避的文化和落后的AI战略等挑战；➂ 英特尔在工艺技术上的投资并未带来显著成果，公司必须对其未来做出艰难的选择。➀ Intel's initial promises under Pat Gelsinger were ambitious but execution has been lacking; ➁ The company faces challenges with a bloated workforce, risk-averse culture, and a lagging AI strategy; ➂ Intel's investments in process technology have not yielded significant results, and the company must make hard choices about its future.
12/03/2024, 07:23 AM UTC
威廉·布克纳学院1月开设14个商业工程学士新课程14 New Study Programs in Bachelor of Business Engineering at Wilhelm Büchner Hochschule Starting January
➀ 威廉·布克纳学院将从1月份开始提供14个商业工程学士新课程；➁ 这些课程旨在为在职学生提供各自职业领域的进一步资格；➂ 课程涵盖了车辆技术、信 息技术、塑料技术、人工智能、食品、物流、机电、医疗技术和工艺技术等多个主题。➀ Wilhelm Büchner Hochschule will offer 14 new study programs in Business Engineering starting from January; ➁ The programs aim to provide working students with further qualifications in their respective professional fields; ➂ The courses cover various topics such as vehicle technology, informatics, plastics technology, artificial intelligence, food, logistics, mechatronics, medical technology, and process technology.
12/02/2024, 06:00 PM UTC
Breker如何帮助解决RISC-V认证问题How Breker is Helping to Solve the RISC-V Certification Problem
➀ RISC-V核心的兴起和认证的挑战；➁ Breker验证系统在认证过程中的作用；➂ 认证RISC-V ISA实现的复杂性以及RISC-V国际组织的努力。➀ The rise of RISC-V cores and the challenges of certification; ➁ The role of Breker Verification Systems in the certification process; ➂ The complexity of certifying RISC-V ISA implementations and the efforts of RISC-V International.
11/27/2024, 06:00 PM UTC
慧荣科技利用GENIO打破3D-IC设计壁垒MZ Technologies is Breaking Down 3D-IC Design Barriers with GENIO
➀ 慧荣科技通过先进的EDA软件GENIO解决2.5D和3D IC设计的复杂挑战；➁ 公司已宣布GENIO的2025年路线图，重点提升热力学应力问题；➂ GENIO旨在促进复杂集成电路系统的设计和优化。➀ MZ Technologies is addressing complex challenges in 2.5D and 3D IC design with advanced EDA software, GENIO; ➁ The company has announced a roadmap for GENIO with enhancements for 2025, focusing on thermal and mechanical stress issues; ➂ GENIO is designed to facilitate the design and optimization of complex IC systems.
11/23/2024, 10:19 AM UTC
您的免费试用Feed URL已于2024年11月23日星期六到期，请创建新的免费URL或升级订阅计划以获得持久URLYour trial feed URL has expired on Sat Nov 23, 2024
➀ 您的免费试用Feed URL已于2024年11月23日星期六到期；➁ 请免费创建新的URL或升级您的订阅计划；➂ 在<a href="https://www.mysitemapgenerator.com/rss/index.html">MySitemapGenerator.com</a>获取持久URL➀ Your trial feed URL has expired on Sat Nov 23, 2024; ➁ Please create a new one for free or upgrade your subscription plan; ➂ Get a persistent URL at <a href="https://www.mysitemapgenerator.com/rss/index.html">MySitemapGenerator.com</a>
11/21/2024, 06:00 PM UTC
与IP供应商的关系：RISC-V与开源功能验证的探讨Relationships with IP Vendors
➀ 与IP供应商沟通时，正确提问和确保功能模型到位的重要性；➁ 验证CPU IP，尤其是高性能设计的挑战；➂ RISC-V在开源生态系统中的作用以及供应商间协作的重要性。➀ The importance of asking the right questions to IP vendors and ensuring functional models are in place; ➁ The challenges of verifying CPU IP, especially high-performance designs; ➂ The role of RISC-V in the open-source ecosystem and the importance of collaboration among vendors.
11/19/2024, 02:00 PM UTC
Alchip引领未来3D设计创新之路Alchip is Paving the Way to Future 3D Design Innovation
➀ Alchip在TSMC OIP生态系统论坛上展示；➁ 克服3D IC设计挑战；➂ 与Synopsys和TSMC合作进行3D设计创新➀ Alchip presents at TSMC OIP Ecosystem Forum; ➁ Challenges in 3D IC design overcome; ➂ Collaboration with Synopsys and TSMC for 3D design innovation
11/18/2024, 06:00 PM UTC
在UVM代码中处理反对意见Handling Objections in UVM Code
➀ 本文讨论了在UVM代码中使用反对意见进行同步。 ➁ 提供了使用uvm_objection的效率示例和替代方法。 ➂ 强调了避免过度使用反对意见以避免减慢仿真速度的重要性。➀ This blog discusses the use of objections in UVM code for synchronization. ➁ It provides examples and alternative approaches to using uvm_objection efficiently. ➂ The importance of not overusing objections to avoid slowing down simulations is emphasized.
11/18/2024, 02:00 PM UTC
基于ANN参数的GaN HEMT建模：提升模型扩展性GaN HEMT modeling with ANN parameters targets extensibility
➀ 探索使用ANN参数改进的ASM-HEMT混合模型进行GaN HEMT建模；➁ 解决了准确拟合宽范围S参数的挑战；➂ 基于ANN的参数拟合减少了测量与模拟之间的差异。➀ An improved ASM-HEMT hybrid model using ANN parameters is explored for GaN HEMT modeling; ➁ The challenge of accurate wide-range S-parameter fit is addressed; ➂ ANN-based parameter fitting reduces the discrepancy between measurements and simulations.
11/14/2024, 06:00 PM UTC
利用AI进行模拟IC迁移Analog IC Migration using AI
➀ 将DRAM芯片在不同工艺节点之间迁移的手动过程是一个挑战；➁ Cadence的Virtuoso Studio工具实现了AI驱动的设计迁移；➂ 基于AI的流程自动化迁移过程，提高了生产力和减少了工程工作量。➀ The manual process of migrating DRAM chips between process nodes is a challenge; ➁ Cadence's Virtuoso Studio tools enable AI-driven design migration; ➂ AI-powered flow automates the migration process, improving productivity and reducing engineering effort.
11/14/2024, 04:00 PM UTC
西门子新一代系统设计工具：电子系统设计的未来Next Generation of Systems Design at Siemens
➀ 介绍西门子新一代电子设计自动化工具；➁ 概述新功能，如统一的图形用户界面、人工智能集成和云连接；➂ 提高工程师生产力和协作的益处；➂ 与其他西门子产品和产品生命周期管理系统的集成➀ Introduction to Siemens' next-generation EDA tools; ➁ Overview of new features like unified GUI, AI integration, and cloud connectivity; ➂ Benefits for engineers in productivity and collaboration; ➃ Integration with other Siemens products and PLM systems
11/12/2024, 06:00 PM UTC
信号完整性基础Signal Integrity Basics
➀ PCB和封装设计中的信号完整性（SI）问题；➁ 波形失真和时间延迟；➂ 信号完整性问题类型，如过冲和ISI；➃ 传输线建模和微带/带状线示例；➄ 最小化不连续性和管理反射；➅ 缓解串扰和过孔性能；➆ 高速数字设计中的时序和偏斜考虑。➀ Signal Integrity (SI) issues in PCB and package design; ➁ Waveform distortions and time delays; ➂ Types of signal integrity problems like overshoot and ISI; ➃ Transmission line modeling and microstrip/stripline examples; ➄ Minimizing discontinuities and managing reflections; ➅ Mitigating crosstalk and via performance; ➆ Timing and skew considerations in high-speed digital designs.
11/12/2024, 02:00 PM UTC
我与Infinisim的对话 - 良好足够不再是足够My Conversation with Infinisim – Why Good Enough Isn’t Enough
➀ 作者讨论了芯片设计分析的彻底重要性，强调了像Infinisim这样的工具在预防潜在故障和最大化性能方面的必要性；➁ Infinisim的联合创始人兼首席技术官Zakir H. Syed博士分享了他们的技术如何解决这些挑战以及行业接受次优性能的趋势；➂ 对话强 调了使用高级工具进行芯片设计的战略价值，以增强盈利能力和竞争力。➀ The author discusses the importance of thorough chip design and analysis, highlighting the need for tools like Infinisim to prevent potential failures and maximize performance; ➁ Infinisim's co-founder and CTO, Dr. Zakir H. Syed, shares insights on how their technology addresses these challenges and the industry's tendency to accept suboptimal performance; ➂ The conversation emphasizes the strategic value of using advanced tools for chip design to enhance profitability and competitiveness.
11/11/2024, 06:00 PM UTC
构建100%基于Python 的大规模SoC设计环境Build a 100% Python-based Design environment for Large SoC Designs
➀ 半导体行业中构建基于Python的设计环境的必要性；➁ Python在SoC设计中的优势；➂ Python在学术界和工业界的应用；➃ Defacto的SoC编译器和其Python API；➄ 使用Python进行RTL代码生成的案例研究。➀ The need for a Python-based design environment in the semiconductor industry; ➁ The advantages of Python in SoC design; ➂ Python's role in academia and industry; ➃ Defacto's SoC Compiler and its Python API; ➄ Case study on using Python for RTL code generation.
11/11/2024, 06:00 PM UTC
芯片研发项目寻求加速创新The Chips R&D Program Seeks to Accelerate Innovation
➀ 《芯片和科学法案》为半导体研发拨款110亿美元；➁ 该项目聚焦于包括先进封装和人工智能驱动设计在内的五个领域；➂ 各公司应立即申请资金机会。➀ The Chips and Science Act allocates $11 billion for semiconductor R&D; ➁ The program targets five areas including advanced packaging and AI-driven design; ➂ Companies should apply now for funding opportunities.
11/09/2024, 10:19 AM UTC
中美芯片战持续，中国芯片制造设备支出或将在2025年降至400亿美元以下 | TrendForce 新闻[News] China’s Chipmaking Equipment Spending Likely to Drop below USD 40 Billion in 2025 amid U.S. Tensions | TrendForce News
➀ 美国总统选举的影响以及中美持续的芯片战争可能使中国半导体设备支出在2025年降至400亿美元以下。➁ 预计这一紧张局势将影响全球半导体供应链。➂ 该情况凸显了国内半导体制造能力的重要性。➀ Concerns over the impact of the U.S. presidential election and the ongoing chip war between China and the U.S. are likely to decrease China's semiconductor equipment spending to below USD 40 billion in 2025. ➁ The tension is expected to affect the global semiconductor supply chain. ➃ The situation highlights the importance of domestic semiconductor manufacturing capabilities.
11/07/2024, 06:00 PM UTC
RISC-V 验证要求、标准化和基础设施的演变Changing RISC-V Verification Requirements, Standardization, Infrastructure
➀ 随着RISC-V架构的普及，其验证要求的演变；➁ 标准化和基础设施在支持RISC-V增长中的作用；➂ 开源功能验证在RISC-V中面临的挑战和机遇。➀ The evolving verification requirements of RISC-V as the architecture gains adoption; ➁ The role of standardization and infrastructure in supporting RISC-V’s growth; ➂ Challenges and opportunities in open-source functional verification for RISC-V.
11/06/2024, 06:00 PM UTC
Synopsys-Ansys 2.5D/3D 多芯片设计更新：从早期采用者那里学习Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters
➀ 高性能计算和AI推动2.5D和3D多芯片设计的兴起；➁ 架构和早期原型设计中的挑战，包括热管理和机械可靠性；➂ 早期验证的重要性，以防止成本高昂的延迟和性能不佳；➃ 人工智能在优化设计流程和结果中的作用；➄ 签署工具对于确保多芯片设计可靠性和持久性的重要性。➀ The rise of 2.5D and 3D multi-die designs driven by high-performance computing and AI; ➁ Challenges in architecture and early prototyping, including thermal management and mechanical reliability; ➂ The importance of early verification to prevent costly delays and suboptimal performance; ➃ The role of AI in optimizing design processes and outcomes; ➄ The significance of sign-off tools for ensuring reliability and longevity of multi-die designs.
11/05/2024, 06:00 PM UTC
功能与安全、安全性和PPA验证的融合The Convergence of Functional with Safety, Security and PPA Verification
➀ 讨论了形式验证的挑战，强调使形式验证可访问和可扩展的重要性。➁ 介绍了Axiomise通过咨询、培训和自动化IP使形式验证变得正常的方法。➂ 介绍了《实用形式验证入门》课程，重点是使形式验证易于理解和应用。➀ The challenges of formal verification are discussed, highlighting the importance of making formal verification accessible and scalable. ➁ Axiomise's approach to making formal verification normal through consulting, training, and automated IP is presented. ➂ The Essential Introduction to Practical Formal Verification course is introduced, focusing on making formal verification easy to understand and apply.
11/05/2024, 04:00 PM UTC
系统内测试的新产品：Siemens的Tessent In-System Test软件New Product for In-System Test
➀ 西门子推出了新的系统内测试控制器ISTC，与Tessent Streaming Scan Network软件配合，实现确定性系统内测试。➁ ISTC支持所有Tessent MissionMode功能，可针对特定的单元内部和老化缺陷进行定位。➂ 新产品旨在解决安全和安全领域以及网络和数据中心的质量问题。➀ Siemens has introduced a new In-System Test Controller, the ISTC, to enable deterministic in-system testing with the Tessent Streaming Scan Network software. ➁ The ISTC supports all Tessent MissionMode features and can target specific cell-internal and aging defects. ➂ The new product addresses challenges in safety and security, as well as quality in networking and data centers.
11/04/2024, 02:00 PM UTC
2024年DVCon欧洲会议亮点回顾Notes from DVCon Europe 2024
➀ 2024年DVCon欧洲会议突出了AI和软件在设计与验证中的兴起。➁ 英飞凌和Zyphra的高峰论坛讨论了AI微控制器架构和数据中心规模AI系统。➂ 软件定义汽车和RISC-V等开源技术也是重要议题。➀ The DVCon Europe 2024 conference highlighted the rise of AI and software in design and verification. ➁ Keynotes from Infineon and Zyphra discussed AI microcontroller architectures and datacenter-scale AI systems. ➃ Software-defined vehicles and open-source technologies like RISC-V were also key topics.
11/01/2024, 12:30 AM UTC
西门子收购EDA新星Altair Engineering[News] Siemens Acquires EDA Rising Star Altair Engineering
➀ 西门子宣布收购Altair Engineering；➁ Altair是EDA行业领先的软件提供商；➂ 收购旨在加强西门子在软件市场的地位。➀ Siemens has announced the acquisition of Altair Engineering; ➁ Altair is a leading software provider in the EDA industry; ➂ The acquisition aims to strengthen Siemens' position in the software market.
10/29/2024, 01:00 PM UTC
如何使用Questa更新您的FPGA设备How to Update Your FPGA Devices with Questa
➀ 介绍更新过时FPGA设 计的挑战；➁ 解释将设计重新定向到新技术的好处；➂ 描述Questa等效FPGA重新定向流程；➃ 提供了三种应用该流程的场景。➀ Introduces the challenge of updating obsolete FPGA designs; ➁ Explains the benefits of retargeting to newer technologies; ➂ Describes the Questa Equivalent FPGA retargeting flow; ➃ Provides three use cases for applying the flow.
10/28/2024, 11:30 PM UTC
高通争议凸显科技巨头定制硅设计对ARM的挑战[News] Qualcomm Dispute Highlights Arm’s Challenge Posed by Tech Giants’ Custom Silicon Designs
➀ 高通与Arm Holdings的争议受到关注；➁ Arm与高通的架构许可协议被终止；➂ 争议反映了科技巨头定制硅设计对Arm提出的挑战。➀ Qualcomm's dispute with Arm Holdings is highlighted; ➁ Arm's architectural license agreement with Qualcomm is terminated; ➂ The dispute reflects the challenges posed by tech giants' custom silicon designs to Arm.
10/24/2024, 05:00 PM UTC
RISC-V与开源功能验证挑战The RISC-V and Open-Source Functional Verification Challenge
➀ RISC-V与开源功能验证挑战探讨了RISC-V和ARM核心验证过程的差异。 ➁ 讨论了选择可靠IP供应商的重要性以及软件支持对验证的影响。 ➂ 强调了RISC-V配置文件在简化验证和实现软件兼容性方面的作用。➀ The RISC-V and open-source functional verification challenge highlights the differences in verification processes between RISC-V and ARM cores. ➁ The importance of selecting a reliable IP vendor and the impact of software support on verification is discussed. ➂ The role of RISC-V profiles in simplifying verification and enabling software compatibility is emphasized.
10/24/2024, 12:00 PM UTC
谷歌或采用台积电N3E工艺替代2nm制造Tensor G6[News] Google Reportedly Adopts TSMC’s N3P Process instead of 2nm for Tensor G6
➀ 据传闻，谷歌将采用台积电的N3E工艺制造Tensor G5；➁ 报告还明确指出，谷歌没有选择为Tensor G6使用2nm技术；➂ 这一举措可能影响AI和智能手机芯片市场的竞争。➀ Google is rumored to switch to TSMC's N3E process for Tensor G5; ➁ The report also clarifies that Google has chosen not to use 2nm technology for Tensor G6; ➂ The move could impact the competition in the AI and smartphone chip markets.
10/22/2024, 05:00 PM UTC
Cadence Sigrity X 在信号完整性与电源完整性分析上的更新SI and PI Update from Cadence on Sigrity X
➀ Cadence 的 Sigrity X 通过分布式模拟克服了信号完整性/电源完整性分析的局限性；➁ Sigrity X 提供了针对 PCB 和 IC 封装设计的各种工具，针对特定任务；➂ Sigrity X 的性能提升高达 10 倍，提高了信号和电源完整性分析的效率。➀ Cadence's Sigrity X utilizes distributed simulation to overcome SI/PI analysis limitations; ➁ Sigrity X offers various tools for specific tasks in PCB and IC package design; ➂ Performance improvements up to 10X faster with Sigrity X, enhancing efficiency in signal and power integrity analysis.
10/21/2024, 05:00 PM UTC
SoC调试挑战解锁：高效原型制作之路Unlocking SoC Debugging Challenges: Paving the Way for Efficient Prototyping
➀ 随着芯片设计的日益复杂，高效的调试解决方案对于成功的原型验证至关重要；➁ 原型制作在芯片验证中扮演着关键角色，它可以通过真实场景测试和早期客户演示来确保可靠性；➂ S2C的Prodigy原型制作解决方案提供了一整套调试平台，包括实时控制软件、设计调试软件、多调试模块和ProtoBridge协同仿真软件等工具。➀ The increasing complexity of chip design necessitates efficient debugging solutions for successful prototype verification; ➁ Prototyping plays a crucial role in chip verification by enabling real-world scenario testing and early customer demonstrations; ➂ S2C's Prodigy prototyping solution offers a comprehensive debugging platform with tools like real-time control software, design debugging software, Multi-Debug Module, and ProtoBridge co-simulation software.
10/17/2024, 05:00 PM UTC
通过早期短路隔离实现更快的SoC验证Prioritize Short Isolation for Faster SoC Verification
➀ 随着SoC设计的复杂性增加，LVS验证中短路问题日益突出；➁ 传统LVS验证和短路调试方法存在诸多挑战；➂ Calibre RVE交互式短路隔离（ISI）流程在高效短路隔离和调试方面的优势；➃ 集成短路隔离提升设计师生产力的途径。➀ The increasing complexity of SoC designs and the challenge of shorted nets in LVS verification; ➁ The challenges of traditional LVS verification and short debugging approaches; ➂ The benefits of the Calibre RVE Interactive Short Isolation (ISI) flow for efficient short isolation and debugging; ➃ The boost in designer productivity through integrated short isolation.
10/16/2024, 01:00 PM UTC
移动LLM不只是技术。实际应用案例才是关键Mobile LLMs Aren’t Just About Technology. Realistic Use Cases Matter
➀ 谷歌正在探索在移动设备上运行大型语言模型（LLM）的可行性；➁ 谷歌在移动设备上优化LLM的技术；➂ 移动设备上LLM实际应用案例的重要性➀ Arm is exploring the feasibility of running LLMs on mobile devices; ➁ Arm's optimization techniques for LLMs on mobile; ➂ The importance of practical use cases for LLMs in mobile devices
10/15/2024, 05:00 PM UTC
电子束探测：7nm以下集成电路安全分析的新守护者Electron Beam Probing: The New Sheriff in Town for Security Analyzing of Sub- 7nm ICs with Backside PDN
➀ 电子束探测（EBP）已成为分析7nm以下集成电路安全性的有效方法。 ➁ 它比光学探测具有更高的空间分辨率，适用于7nm以下的倒装芯片和先进的三维架构。 ➂ 研究重点在于EBP在故障分析和硬件保证中的重要性。➀ Electron Beam Probing (EBP) has become a powerful method for security analyzing of sub-7nm ICs. ➁ It offers better spatial resolution than optical probing and is suitable for sub-7nm flip-chips and advanced 3D architectures. ➂ The research focuses on the importance of EBP in failure analysis and hardware assurance.
10/15/2024, 01:00 PM UTC
现代IC设计中非传统形状的阻抗提取导航Navigating resistance extraction for the unconventional shapes of modern IC designs
➀ 由于物联网、图像传感器和3DICs的兴起，IC设计的复杂性；➁ 非曼哈顿布线和非常规形状的阻抗提取的挑战；➂ 准确的阻抗提取对于设计可靠性和演进的破 碎技术的重要性。➀ The complexity of IC design due to the rise of IoT, image sensors, and 3DICs; ➁ Challenges in resistance extraction for non-Manhattan routing and unconventional shapes; ➂ The importance of accurate resistance extraction for design reliability and evolving fracturing techniques.
10/11/2024, 01:00 PM UTC
LUBIS EDA CEO 托比亚斯·路德维希访谈CEO Interview: Tobias Ludwig of LUBIS EDA
➀ 托比亚斯·路德维希讨论了他电子设计自动化领域的旅程以及LUBIS EDA的创立；➁ 传统形式化验证过程中存在的挑战 和低效性；➂ LUBIS EDA使用AI技术自动化和简化形式化验证的创新方法。➀ Tobias Ludwig discusses his journey in electronic design automation and the founding of LUBIS EDA; ➁ The challenges and inefficiencies in traditional formal verification processes; ➂ LUBIS EDA's innovative approach to automating and simplifying formal verification using AI techniques.
10/08/2024, 05:00 PM UTC
通过3DBlox最大化3D集成电路设计生产力：TSMC在2024年的进展和创新Maximizing 3DIC Design Productivity with 3DBlox: A Look at TSMC’s Progress and Innovations in 2024
➀ TSMC的3DBlox框架解决了3DIC设计的复杂性；➁ 2024年的创新重点在于简化3D设计挑战；➂ TSMC在管理3DIC系统中的电气和物理约束方面的策略。➀ TSMC's 3DBlox framework addresses complexities in 3DIC design; ➁ Innovations in 2024 focus on simplifying 3D design challenges; ➂ TSMC's strategies for managing electrical and physical constraints in 3DIC systems.
09/26/2024, 05:00 PM UTC
利用高级数据分析自动化重置域跨越（RDC）验证Automating Reset Domain Crossing (RDC) Verification with Advanced Data Analytics
➀ 随着SoC设计复杂性的增加，RDC验证变得更具挑战性；➁ 数据分析技术可以自动化RDC验证，减少手动分析并提高效率；➂ 案例研究显示，通过数据驱动分析显著减少了RDC违规。➀ The complexity of SoC designs continues to rise, making RDC verification challenging; ➁ Data analytics techniques can automate RDC verification, reducing manual analysis and improving efficiency; ➂ Case study shows a significant reduction in RDC violations through data-driven analysis.
09/23/2024, 05:49 PM UTC
LPKF否认Philoptics对其TGV技术的指控：提供有限孔径尺寸LPKF denies Philoptics’ allegation that its TGV tech offers limited hole sizes
➀ LPKF驳斥Philoptics对其TGV技术的指控；➁ Philoptics声称LPKF的技术只能提供有限孔径尺寸；➂ LPKF对Philoptics关于技术优越性的指控提出异议。➀ LPKF refutes Philoptics' claims about its TGV technology; ➁ Philoptics alleged LPKF's technology offers limited hole sizes; ➂ LPKF disputes Philoptics' claim of technological superiority.
07/18/2024, 01:00 PM UTC
EDA中原型设计的演变Evolution of Prototyping in EDA
1、AI和5G技术的快速发展正在推动芯片行业，特别是SoC设计的演变。2、原型设计，尤其是基于FPGA的，由于其速度和成本效益，已成为验证复杂SoC的关键。3、Synopsys、Cadence和Siemens EDA等主要EDA公司已进入原型设计市场，提高了SoC设计的效率和准确性。1. The rapid growth of AI and 5G technologies is driving the evolution of the chip industry, particularly in SoC design. 2. Prototyping, especially FPGA-based, has become essential for verifying complex SoCs due to its speed and cost-effectiveness. 3. Major EDA companies like Synopsys, Cadence, and Siemens EDA have entered the prototyping market, enhancing efficiency and accuracy in SoC designs.
07/11/2024, 05:00 PM UTC
谁将成为DAC的下一批主要租户？Who Are the Next Anchor Tenants at DAC? #61DAC
1. #61DAC的演变中，传统的EDA公司如Cadence和Synopsys正在缩减展位，而像Altair这样的新进入者正在迅速获得动力。2. 拥有模拟、AI、高性能计算和数据分析等全面解决方案的Altair，有望成为DAC的主要租户。3. Altair通过持续的收购和合作策略，正将自己定位为电子系统市场的领导者。1. The evolution of #61DAC sees traditional EDA companies like Cadence and Synopsys downsizing their presence, while new entrants like Altair are gaining momentum. 2. Altair, with its comprehensive solutions in simulation, AI, HPC, and data analytics, is poised to become a key anchor tenant at DAC. 3. Altair's strategy includes continuous growth through acquisitions and partnerships, positioning itself as a leader in the electronics systems market.
07/01/2024, 01:00 PM UTC
EDA与芯片设计职业选择：解决困境Career in EDA Versus Chip Design: Solving the Dilemma
1、文章比较了芯片设计和EDA领域的职业，强调了作者从芯片设计转向领导Ansys应用工程团队的经历。2、概述了EDA职业的优势，包括技术曝光、跨团队合作、商业洞察、工作文化和行业稳定性。3、由于AI和机器学习领域对EDA工具的依赖增加，EDA的未来被视为光明。1. The article compares careers in chip design and EDA, highlighting the author's transition from chip design to leading an Application Engineering team at Ansys. 2. It outlines the advantages of an EDA career, including technical exposure, cross-team collaboration, business acumen, work culture, and industry stability. 3. The future of EDA is seen as bright due to the increasing reliance on EDA tools in areas like AI and Machine Learning.
06/19/2024, 03:00 PM UTC
Agnisys在2024年设计自动化会议上的展示Agnisys at the 2024 Design Automation Conference
1、Agnisys作为硬件设计和验证自动化领域的领导者，将在2024年DAC上通过多种活动产生重大影响。2、公司赞助了'I LOVE DAC'，并提供44个优惠码，用于访问会议的高级工程轨道。3、Agnisys举办了一个设计竞赛，展示其IDS-NG工具在数字设计中的效率。1. Agnisys, a leader in hardware design and verification automation, is set to make a significant impact at DAC 2024 with various engaging activities. 2. The company is sponsoring 'I LOVE DAC' and offering 44 promo codes for premium Engineering Tracks. 3. Agnisys is hosting a design contest featuring its IDS-NG tool, showcasing its efficiency in digital design.
06/03/2024, 01:00 PM UTC
Synopsys为处理器生态系统提供广泛支持Follow the Leader – Synopsys Provides Broad Support for Processor Ecosystems
1、Synopsys扩展了ARC处理器产品系列，包括RISC-V处理器系列。 2、Synopsys为处理器生态系统提供holistic支持，包括实现、验证、软件开发、DevOps等。 3、Synopsys与Arm和RISC-V核心提供商等合作，提供了广泛的解决方案。
05/08/2024, 05:00 PM UTC
Synopsys 开创成功之路：112G SerDes 及其以后Synopsys is Paving the Way for Success with 112G SerDes and Beyond
Data communication speeds continue to grow. New encoding schemes, such as PAM-4 are helping achieve faster throughput. Compared to the traditional NRZ scheme, PAM4 can send twice the signal by using four levels vs. the two used in NRZ. The diagram at the top of this post shows the how data density is increased. With progress comes… Read More The post Synopsys is Paving the Way for Success with 112G SerDes and Beyond appeared first on SemiWiki.
05/03/2024, 08:30 PM UTC
Samsung Tapes Out Its First 3nm Smartphone SoC, Gets A Boost From Synopsys AI-Enabled Tools
This week Samsung Electronics and Synopsys announced that Samsung has taped out its first mobile system-on-chip on Samsung Foundry's 3nm gate-all-around (GAA) process technology. The announcement, coming from electronic design automation Synopsys, further notes that Samsung used the Synopsys.ai EDA suite to place-n-route the layout and verify design of the SoC, which in turn enabled higher performance. Samsung's unnamed high-performance mobile SoC relies on 'flagship' general-purpose CPU and GPU architectures as well as various IP blocks from Synopsys. SoC designers used Synopsys.ai EDA software, including the Synopsys DSO.ai to fine-tune design and maximize yields as well as Synopsys Fusion Compiler RTL-to-GDSII solution to achieve higher performance, lower power, and optimize area (PPA). And while the news that Samsung has developed a high-performance SoC using the Synopsys.ai suite is important, there is another, even more important dimension to this announcement: this means that Samsung has finally taped out an advanced smartphone application processor on its cutting-edge 3nm GAAFET process. Although Samsung Foundry has been producing chips on its GAA-equipped SF3E (3 nm-class, 'early' node) process for almost two years now, Samsung Electronics has never used this technology for its own system-on-chips for smartphones or other complex devices. To date, SF3E has been used mainly for cryptocurrency mining chips, presumably due to the inevitable early teething and yield issues that come with being the industry's first commercial GAAFET process. For now, Samsung isn't disclosing what specific process node is being used for the SoC; the official Samsung/Synposys announcement only notes that it's for a GAA process node. Along with their first-generation 3nm-class SF3E, Samsung Foundry has a considerably more sophisticated SF3 manufacturing technology that offers numerous improvements over SF3E, and is due to be used for mass production in the coming quarters. Given th
04/30/2024, 01:00 PM UTC
Enabling Imagination: Siemens’ Integrated Approach to System Design
In today’s rapidly advancing technological landscape, semiconductors are at the heart of innovation across diverse industries such as automotive, healthcare, telecommunications, and consumer electronics. As a leader in technology and engineering, Siemens plays a pivotal role in empowering the next generation … Read More The post Enabling Imagination: Siemens’ Integrated Approach to System Design appeared first on SemiWiki.
