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January 6
- Can LELE Multipatterning Help Against EUV Stochastics?➀ Stochastic effects below 50 nm pitches require reevaluation of EUV lithography resolution limits; ➁ LELE multipatterning does not sufficiently mitigate stochastic effects due to small critical dimensions; ➂ Comparative performance analysis shows slight improvement at 60 nm pitch, but stochastic defect rates remain an issue.
January 3
- WEBINAR: 2025 Semiconductor Year in Preview➀ TechInsights offers a preview of the 2025 semiconductor industry with a free webinar; ➁ Discusses major trends like tariff changes, AI accelerators, and 2nm technology breakthroughs; ➂ Features presentations by TechInsights experts on key industry events and implications.
- Accelerating Automotive SoC Design with Chiplets➀ The automotive industry is rapidly evolving towards intelligent, connected, and autonomous vehicles with SoC technology; ➁ Chiplet-based architectures offer modular, scalable, and customizable solutions for automotive SoC design; ➂ Cadence provides tools and frameworks to enhance the design process and ensure safety, performance, and reliability.
January 2
- AI PC momentum building with business adoption anticipated➀ The AI PC market is expected to grow significantly with business adoption; ➁ AI PCs offer advantages for personal and business use, including data analysis and productivity; ➂ Designers face challenges in providing sufficient computing power and battery life, and the need for scalable NPU solutions.
January 1
- Happy New Year from SemiWiki➀ SemiWiki celebrates its 14th anniversary; ➁ The author reflects on his journey in the semiconductor industry; ➂ The evolution of SemiWiki from a blog to a leading industry platform.
- CEO Interview: Subi Krishnamurthy of PIMIC➀ PIMIC is an AI semiconductor startup focusing on ultra-low-power AI solutions with innovative processing-in-memory (PiM) technology. ➁ The company plans to launch two ultra-efficient AI silicon chips at CES 2025 with 10x to 20x power savings. ➂ PIMIC's Jetstreme™ Processing-in-Memory architecture addresses the increasing demand for performance in small to large AI models.
December 31
- Intel and the IFS Dilemma: Stuck Between a Rock and a Hard Place – Should They attempt to Sell Intel Foundry Services➀ Intel's Foundry Services (IFS) division is struggling with low wafer yields and projected cumulative losses. ➁ Selling IFS could provide Intel with $30 billion to focus on core operations, but might hinder IDM 2.0 strategy. ➂ The decision hinges on whether Intel should continue investing in IFS or sell it to reduce financial risks.
December 30
- Accelerating Simulation. Innovation in Verification➀ This article discusses the research on accelerating RTL simulation with hardware-software co-design; ➁ It compares the performance of Chronos and SASH, the latest advancements in hardware acceleration for RTL simulation; ➂ The article explores the potential impact of these technologies on the EDA industry.
December 27
- The Intel Common Platform Foundry Alliance➀ Intel needs to fill its fabs to remain competitive; ➁ TSMC's rapid expansion with new partnerships; ➂ The potential of a Common Foundry Platform Alliance for Intel.
- CEO Interview: Marc Engel of Agileo Automation➀ Agileo Automation specializes in software solutions for semiconductor production equipment control and MES system integration; ➁ Marc Engel has 25 years of engineering experience in software development and equipment setup; ➂ The company's A²ECF-SEMI framework helps customers reduce time-to-market; ➃ Agileo Automation focuses on customer experience and service.
December 26
- CEO Interview with Dr. Dennis Michaelis of GEMESYS➀ GEMESYS focuses on AI hardware with an analog chip architecture for energy-efficient neural network processing on edge devices; ➁ The company addresses industry challenges like high energy consumption in AI model training and focuses on data privacy; ➂ GEMESYS targets application areas like consumer electronics, automotive, healthcare, and industrial IoT with its innovative technology.
December 25
- CEO Interview: Dr Josep Montanyà of Nanusens➀ Nanusens CEO Dr. Josep Montanyà discusses the company's patented NEMS technology and its applications in sensors and AI processors; ➁ The company's focus on RF DTC and its potential to revolutionize smartphone technology; ➂ Challenges faced in fundraising and the company's strategic shift to focus on RF products; ➃ The potential of vacuum transistors in AI processors and Nanusens' plans for future development.
- Stochastic Pupil Fill in EUV Lithography➀ EUV光刻受随机效应影响，导致吸收光子数量变化，可能产生缺陷；➁ EUV系统的随机照明角度导致光子分布不均，造成图像偏移和精确光刻图案的挑战；➂ 减少pupil填充可以缓解随机失真，但会严重限制光刻系统的吞吐量。
December 24
- What would you do if you were the CEO of Intel?➀ Intel's shift to a more transparent strategy in technology announcements; ➁ The competition between Intel's PowerVia and TSMC's Super Power Rail; ➂ Andy Grove's philosophy of maintaining a 'healthy amount of paranoia'.
- Consumer memory slowing more than AI gaining➀ Micron reports revenue and EPS in line with expectations but provides weak guidance; ➁ AI-driven memory demand surges, while consumer memory struggles; ➂ Market concerns over Micron's stock due to the imbalance between AI and consumer memory growth.
December 20
- If you believe in Hobbits you can believe in Rapidus➀ Semicon Japan exhibit high attendance but a muted tone due to concerns over spending; ➁ Rapidus, a Japanese government-backed semiconductor plan, is seen as a fantasy; ➂ Analysts are adjusting their 2025 WFE outlook due to slowing demand; ➃ Chip equipment companies are lobbying for China sales, raising questions about hypocrisy; ➄ Stock market instability and uncertainty about the new administration's semiconductor policies.
- TSMC Unveils the World’s Most Advanced Logic Technology at IEDM➀ TSMC unveiled its 2nm Platform Technology at IEDM, featuring GAA nanosheet transistors for AI, HPC, and mobile applications. ➁ The N2 technology achieves significant improvements in speed and power efficiency compared to the 3nm node. ➂ TSMC's N2 is scheduled for mass production in 2025, with an enhanced version, N2P, targeted for 2026.
December 19
- Ultra Ethernet and UALink IP solutions scale AI clusters➀ The growing demand for AI infrastructure requires scalable interconnects; ➁ Ultra Ethernet and UALink address the challenges of scaling AI acceleration clusters; ➂ Synopsys' IP solutions offer efficient and power-efficient interconnects for data centers.
- Reset Domain Crossing (RDC) Challenges➀ The complexities of modern IC designs with multiple clocks and asynchronous resets make reset logic more challenging than in early single-clock designs; ➁ Reset Domain Crossing (RDC) tools, like Questa RDC, perform static verification on reset logic to identify issues like glitches and metastability; ➂ Siemens' Questa RDC is effective in identifying structural and advanced reset tree issues, ensuring integrity before tapeout.
December 18
- ML and Multiphysics Corral 3D and HBM➀ 3D design with HBM is critical for advanced semiconductor systems; ➁ Large system designs require multi-chiplet integration; ➂ Multiphysics and ML are essential for optimizing performance and reliability.
- Intel – Everyone’s Favourite Second Source?➀ The author argues that Intel is not crucial to the industry's success and can be replaced; ➁ Intel faces challenges from competition and the decline of the x86 market; ➂ The author suggests splitting Intel into product and foundry entities to improve focus.
December 17
- MCUs Are Now Embracing Mainstream NoCs➀ The shift in MCU design from simple to complex, requiring more sophisticated interconnects like NoC; ➁ The factors driving this change, including power reduction, safety standards, and support for multiple protocols; ➂ The importance of scalability in design and how NoC architectures can support this.
- An Invited Talk at IDEM: Intel’s Mr. Transistor Presents The Incredible Shrinking Transistor – Shattering Perceived Barriers and Forging Ahead➀ Dr. Tahir Ghani discussed the impact of Moore's Law and the challenges of energy efficiency in semiconductor technology. ➁ He highlighted the evolution of transistor technology over six decades. ➂ He advocated for new transistor designs and collaborations to improve energy efficiency for AI computing.
December 13
- CEO Interview: Caroline Guillaume of TrustInSoft➀ TrustInSoft specializes in advanced software analysis tools for formal verification of C and C++ code; ➁ The company's tools significantly reduce time spent on bug detection and verification; ➂ TrustInSoft uses formal methods to ensure safety, security, and reliability in software.
- IEDM Opens with a Big Picture Keynote from TSMC’s Yuh-Jier Mii➀ TSMC's Mii presented a keynote at the 70th IEDM, discussing the semiconductor industry's growth and the impact of AI, predicting a revenue of one trillion dollars by 2030. ➁ He highlighted the evolution of logic technologies and introduced CFET architectures. ➂ He discussed the importance of advanced silicon stacking and packaging technologies.
- Thanks for the Memories➀ The WSTS forecasts a 19% growth in the semiconductor market for 2024, primarily driven by a 81% growth in the memory segment; ➁ Companies in the automotive and industrial sectors are experiencing revenue declines; ➂ Nvidia's revenue grew 135% due to AI processors, while memory companies reported substantial revenue gains.
December 12
- CEO Interview: Mikko Utriainen of Chipmetrics➀ Chipmetrics is a Finnish company specializing in metrology solutions for high aspect ratio 3D chips; ➁ They provide test chips to accelerate R&D and process control workflows; ➂ The company's PillarHall test chips enable precise measurements of film properties in high aspect ratio cavities.
- How I learned Formal Verification➀ Bing Xue discusses his journey into Formal Verification; ➁ Challenges faced in learning FV without structured courses; ➂ Benefits of Axiomise FV courses in understanding and applying FV techniques.
December 11
- Electrical Rule Checking in PCB Tools➀ Introduces the challenges in PCB design and verification; ➁ Highlights the features of HyperLynx DRC by Siemens; ➂ Discusses the area-crop function and its benefits in PCB design verification; ➃ Provides a case study of MediaTek using HyperLynx DRC for complex PCB design verification.
December 10
- Synopsys Brings Multi-Die Integration Closer with its 3DIO IP Solution and 3DIC Tools➀ Synopsys addresses the challenges of multi-die integration with its 3DIO IP Solution and 3DIC tools; ➁ The 3DIO IP Solution includes synthesis-friendly Tx/Rx cells and a high data rate solution; ➂ Synopsys' tools enable faster timing closure and reduced bit error rates in multi-die designs.