➀ RED Semiconductor launched Ordo1, an AI and flow control accelerator IP core for RISC-V processors, targeting energy-efficient edge AI applications;

➁ The IP core claims 500% acceleration in matrix-heavy workloads and over 90% power reduction compared to standard RISC-V, while requiring 100 times less code;

➂ Backed by partnerships with Aion Silicon and Codasip, plus Seed+ funding, RED joined RISC-V International to align with open standards and expand commercialization.

➀ Upbeat Technology and SiFive collaborate on a dual-core RISC-V MCU family (UP201/UP301) featuring AI accelerators for ultra-low-power edge AI applications.

➀ Delivers 16.8 μW/MHz/DMIPS energy efficiency, 400 MHz clock speed, and advanced error correction for resilient near-threshold operation in wearables, drones, and IoT systems.

➂ Live demos at RISC-V Summit highlight performance, with engineering samples and SDKs available to enable next-gen battery-optimized AI designs.

➀ RISC-V achieves 25% market penetration ahead of schedule, with projections of exceeding 21 billion chips and $2 billion in revenue by 2031;

➀ The open-standard ISA model enables free access and customization, contrasting sharply with ARM’s licensing-centric approach;

➂ Edge AI and adoption by tech giants like Google, AWS, and Meta drive rapid growth, while RISC-V’s extensibility fosters embedded innovation.

➀ Yuning Liang, founder of DeepComputing, pioneered a modular RISC-V laptop design enabling component upgrades, driven by his software-to-hardware career shift and partnerships with companies like Framework.

➁ The project faced technical and geopolitical motivations, leveraging RISC-V to bypass chip trade restrictions and fostering open-source hardware collaboration, though early prototypes like the $5,000 Roma laptop faced financial challenges.

➂ Key hurdles include software ecosystem gaps (e.g., Chromium’s lack of native RISC-V support) and scaling efforts through community-driven initiatives like RISE to integrate RISC-V into mainstream infrastructure.

➀ SiFive launches second-generation RISC-V Intelligence cores (X100/X200/X300/XM) for edge to data center AI workloads, emphasizing high performance and low power consumption;

➁ The X-Series cores function as standalone AI inference processors or accelerator control units, outperforming Arm's Cortex-M85 by up to 230% in MLPerf Tiny benchmarks;

➂ Innovations include hardware exponential acceleration, enhanced memory architecture, and a complete AI software stack supporting TensorFlow/PyTorch integration.

➀ SiFive launched its 2nd Gen Intelligence Family of RISC-V CPUs tailored for AI applications, featuring smaller sizes, lower power consumption, and enhanced accelerator IP integration;

➁ The new series includes X100/X200/X300/XM models with RVA23 standardization for improved software compatibility, and introduces dual interfaces (SSCI/VCIX) to optimize accelerator control;

➂ Architectural innovations like configurable cache hierarchy and optimized exponential functions aim to boost performance for AI accelerators while maintaining flexibility in embedded and large-scale systems.

➀ High-performance CPU design is transitioning from traditional Out-of-Order (OOO) architectures to Time-Based OOO, leveraging RISC-V's open ecosystem to improve power efficiency and scalability.

➁ Condor Computing's Cuzco processor uses a slice-based microarchitecture and predictive scheduling via a Time Resource Matrix, enabling flexible configurations for datacenter, mobile, and automotive applications.

➂ Key advantages include superior performance-per-watt, simplified verification, and ISA extensibility, positioning RISC-V as a competitive alternative to legacy architectures like x86 and ARM.

➀ Basilisk is a groundbreaking RISC-V SoC developed with fully open-source EDA tools, demonstrating Linux capability on industrial-grade silicon via mature 130nm BiCMOS process；

➁ The project challenges traditional IP/EDA business models, highlighting U.S. incumbents' innovation stagnation versus rapid progress in Europe and China pursuing sovereign chip ecosystems；

➂ Open-source tools like Yosys and OpenROAD achieved silicon success with 64-102MHz operation, GPU-like voltage scalability, and energy efficiency optimization, enabling next-gen 22nm FD-SOI designs

➀ GlobalFoundries (GF) has solidified its role as a leading contract semiconductor manufacturer, focusing on automotive, IoT, and autonomous systems with mature technologies like FD-SOI and FinFET.

➁ GF reported strong Q2 2025 revenue of $1.688 billion, driven by strategic partnerships and acquisitions, including MIPS Technologies to expand RISC-V IP for AI applications.

➂ Despite market volatility and geopolitical risks, GF emphasizes sustainability and regional strategies (e.g., 'China-for-China') to secure its position as the third-largest pure-play foundry globally.

➀ S2C demonstrated comprehensive digital EDA solutions and strategic partnerships at RISC-V Summit China 2025, supporting IP validation to system-level verification;

➁ Live demos included BOSC's 16-core Kunminghu processor validated using S8-100Q systems and Xuantie R908 real-time processor implementation;

➂ Introduced Transaction-Based Acceleration methodology combining virtual prototyping and hardware emulation to overcome RISC-V verification challenges.

➀ The RISC-V-based XiangShan project demonstrates high performance through modular design and proven speculative execution techniques, achieving competitiveness comparable to ARM cores.

➁ While XiangShan excels in open-source tooling and iterative development, it adheres to traditional CPU paradigms, inheriting speculative execution's energy and security drawbacks.

➂ Alternative models like Simplex Micro's predictive execution offer a speculation-free architecture, challenging RISC-V's potential to redefine CPU design beyond legacy constraints.

➀ Silicon Creations' low-area PLL technology integrates with Codasip's test chip for evaluating L31AS dual-core CPU and crypto accelerator;

➁ Collaboration advances automotive safety-critical systems using RISC-V cores and analog IP;

➂ PLL's compact design addresses space-sensitive automotive applications while ensuring reliability

➀ Akeana demonstrates leadership in high-performance RISC-V-based SMT IP cores, addressing compute density challenges in edge AI and automotive sectors;

➁ Their SMT implementation supports up to 4 threads per core across three product series, enhancing resource utilization and system efficiency;

➂ SMT enables safety redundancy in automotive systems and performance gains (20-30% Spec score uplift) while reducing chip area and power consumption.

➀ NVIDIA announces CUDA platform support for RISC-V ISA at 2025 RISC-V Summit China, marking the first open-source architecture integrated into its AI ecosystem;

➀ RISC-V CPUs can now serve as main processors in CUDA-based systems, enabling edge computing solutions like Jetson modules and potential datacenter applications;

➁ The move strategically strengthens NVIDIA's position in China's semiconductor market amid U.S. export restrictions, while fostering heterogeneous computing architectures combining RISC-V CPUs, GPUs, and DPUs.

➀ Codasip launched Codasip Prime, a pre-silicon platform integrating CHERI technology to enhance memory safety and security in RISC-V-based systems;

➁ The platform includes FPGA hardware, a software development kit, and CHERI-specific IP to enable secure software development and compliance with regulations like the EU Cyber Resilience Act;

➂ CHERI addresses 87% of memory-related cyberattacks, offering cost-effective protection without requiring full software rewrites, with Codasip collaborating with the CHERI Alliance to standardize RISC-V extensions.

➀ Over 250 billion Arm chips have been shipped since 1985, powering devices from handhelds to datacenters;

➁ ARM1's 3μm/6,000-gate RISC design pioneered energy efficiency through resource constraints, evolving to 3nm/100M+ gates today;

➂ While maintaining dominance in mobile and expanding to AI/datacenters, Arm faces challenges from RISC-V and China's semiconductor ambitions.

Chinese researchers have built a 32-bit RISC-V processor using molybdenum disulfide (MoS2) on a sapphire substrate. The processor, RV32-WUJI, has 6000 transistors and operates at KHz speeds, executing the full RISC-V 32-bit instruction set. The researchers used machine learning to optimize the wiring and materials for the transistors. The overall yield was over 99.9 percent, with a chip-level yield of 99.8 percent.

➀ There has been a significant shift towards RISC-V architectures in SoC design;

➁ This article highlights the impact of this shift on the semiconductor industry;

➂ It discusses the role of RISC-V in fostering innovation and flexibility in technology development.

➀ Axelera AI, founded in 2021, aims to provide scalable edge AI hardware and software solutions.

➁ The company has raised USD 120 million and has a world-class team of over 190 employees.

➂ Axelera AI's Metis platform offers high performance with low power consumption, targeting applications like computer vision, automotive, and healthcare.

➀ A roundup of the latest electronics news from Embedded World 2024, covering automotive, military, telecoms, industrial, and consumer electronics sectors.

➁ Infineon is launching a RISC-V starter kit for automotive microcontrollers.

➂ NXP reveals MCX MCUs with Matter, Thread, Zigbee, and Bluetooth LE.