Recent #Interconnect news in the semiconductor industry

2 months ago

➀ Samtec launches military/aerospace development and evaluation kits based on VITA standards for design validation from prototype to production;

➀ Kits include FMC, FMC+, and FireFly solutions supporting up to 140Gbps bandwidth and 25/28Gbps testing, compatible with FPGA systems;

➂ Products meet MIL-Spec certifications and undergo rigorous environmental testing for harsh applications, including space-grade connectors for satellites.

Interconnectdevelopment kit
3 months ago

➀ Anglia Components signed a franchise agreement with UK-based Winslow Adaptics, expanding its offerings in IC sockets, adapters, and semiconductor hardware solutions;

➁ Winslow's expertise in obsolescence management, reverse engineering, and custom interconnect solutions was highlighted as key to addressing customer needs;

➂ The partnership aims to provide end-to-end design and manufacturing support for Anglia's UK and EU clients, with products now available on Anglia's eCommerce platform.

Interconnectsemiconductor
10 months ago

➀ Marvell's market capitalization surpassed $100 billion for the first time after releasing its Q3 fiscal year 2025 financial results;

➁ Marvell's ASIC business is a key driver of its growth, with over 2,000 custom chips designed over 25 years;

➂ Marvell's custom AI chip services are becoming a major revenue source, with significant partnerships and a goal of capturing 20% of the $40 billion custom chip market in data centers;

➃ Marvell's interconnect business is growing rapidly, with advancements in PAM4 SerDes technology and optical interconnect solutions;

➄ Marvell's 3nm optical DSP and 5nm PCIe retimer products are set to drive future growth;

➅ Marvell's 51.2T Ethernet switch, Teralynx 10, is designed for low power and high performance in data center environments;

➆ Marvell's focus on AI and data center technologies is expected to continue driving growth and market capitalization.

ASICInterconnectMarvellsemiconductor
about 1 year ago
➀ UCIe is an open, multi-protocol interconnect standard for connecting multiple chips within the same package, aiming to support a vibrant ecosystem for disaggregated chip architectures. ➁ It supports various protocols including PCIe, CXL, and Streaming, and allows for the mapping of any chosen protocol as long as both ends support it. ➂ UCIe includes elements necessary for SoC construction and package-related features such as bump placement and thermal solutions. ➃ The UCIe manageability architecture provides a standardized test and debugging infrastructure for UCIe-based SiPs. ➄ UCIe supports three packaging options: standard (2D), advanced (2.5D), and UCIe-3D, catering to a range of performance and cost requirements.
Interconnectsemiconductortechnology