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August 10
- CEO Interview with Bob Owen of Owens Design
➀ Owens Design has delivered over 3,000 custom systems across semiconductor, biomedical and energy sectors with 100% on-time delivery record;
➁ Its PR:IME platform accelerates semiconductor inspection tool development 40% faster through modular design and pre-validated components;
➂ The company operates as an engineering partner bridging R&D and production with phased development approach minimizing technical risks.
- CEO Interview with Karim Beguir of InstaDeep
➀ InstaDeep's DeepPCB leverages AI and reinforcement learning to revolutionize PCB design, tackling manual routing challenges and optimizing efficiency;
➁ The cloud-based solution complements existing EDA tools, offering DRC-clean layouts and accelerating time-to-market for complex PCB designs;
➂ Competing with traditional auto-routers and AI-driven startups, DeepPCB focuses on scalability and accessibility through API integration and community engagement.
August 8
- Making Intel Great Again!
➀ Intel's interim CEO Lip-Bu Tan advocates abandoning solitary IDM model, shifting to a collaborative foundry approach inspired by TSMC;
➁ Samsung secures $16.5B Tesla chip deal through geographic advantages, while Intel faces urgency to secure hero customers for 14A process within 18 months;
➂ Semiconductor industry calls for cross-sector collaboration involving politicians, tech giants and capital to maintain US leadership in advanced manufacturing.
August 7
- Agentic AI and the EDA Revolution: Why Data Mobility, Security, and Availability Matter More Than Ever
➀ Agentic AI is revolutionizing EDA and semiconductor industries by addressing chip design complexity and engineer shortages through autonomous problem-solving;
➁ NetApp's ONTAP and FlexCache ensure data security, real-time synchronization, and hybrid cloud flexibility for AI-driven workflows;
➂ Hybrid cloud infrastructure is critical for scaling AI resources, with NetApp positioning itself as a leader in enabling future-ready EDA solutions.
- WEBINAR: What It Really Takes to Build a Future-Proof AI Architecture?
➀ Incorporating AI at the edge requires purpose-built inference chips to address power and size constraints, with NPUs emerging as key solutions.
➁ Future-proof AI architectures must balance scalability, extendability, and efficiency, as demonstrated by Ceva’s NeuPro-M processor design.
➂ Misleading metrics like IPS and power consumption necessitate holistic evaluation, emphasizing software toolchains and adaptive hardware design.
August 6
- What is Vibe Coding and Should You Care?
➀ Vibe coding is an LLM-driven rapid prototyping method for app interfaces, emphasizing speed over code quality;
➁ While promoted as a playful tool by AI experts like Andrej Karpathy, critics warn of security risks and its misuse in production environments;
➂ Current adaptations position it as a supplementary development aid, but concerns persist about blurred boundaries between experimentation and professional development.
August 5
- Unlocking Efficiency and Performance with Simultaneous Multi-Threading
➀ Akeana demonstrates leadership in high-performance RISC-V-based SMT IP cores, addressing compute density challenges in edge AI and automotive sectors;
➁ Their SMT implementation supports up to 4 threads per core across three product series, enhancing resource utilization and system efficiency;
➂ SMT enables safety redundancy in automotive systems and performance gains (20-30% Spec score uplift) while reducing chip area and power consumption.
- DAC TechTalk – A Siemens and NVIDIA Perspective on Unlocking the Power of AI in EDA
➀ The DAC event highlighted Siemens and NVIDIA's collaboration to integrate AI into EDA tools, addressing semiconductor design complexity and efficiency challenges.
➁ Siemens introduced its AI-driven EDA system for enhanced design workflows, while NVIDIA showcased CUDA-X libraries and NeMo frameworks to accelerate AI adoption in chip design.
➂ The partnership emphasizes AI's role in improving productivity, with NVIDIA's inference microservices and Siemens' domain-specific AI models targeting PCB and IC design optimization.
August 4
- Digital Implementation and AI at #62DAC
➀ Siemens' Aprisa AI tool reduces SoC timing closure from 10-12 weeks to 1-2 weeks, achieving 3X compute efficiency and 10% PPA improvements;
➁ AI addresses industry challenges like 3D IC complexity and rising costs, enabling 6-9 month design cycles (vs. 12-18 months) and addressing engineering shortages through accelerated training;
➂ Agentic AI and cloud-based EDA tools are emerging as future trends, with Siemens showcasing natural language interfaces for clock tree generation and customizable LLM integration.
- Synopsys Webinar – Enabling Multi-Die Design with Intel
➀ Synopsys and Intel collaborated on addressing multi-die design challenges through advanced EDA tools and methodologies;
➁ The webinar highlighted Synopsys' 3DIC Compiler platform for streamlined multi-die design workflow and Intel's insights on 3D IC planning and core folding;
➂ Early design prototypes and tool automation were emphasized as critical for scaling heterogeneous chip integration.
August 3
- A Semiconductor Equipment Pause Coming?
➀ Lam Research reported strong Q2 results with revenue of $5.17B and EPS of $1.33, but expects flat H2 performance and an uncertain 2026 outlook.
➁ China accounts for 35% of Lam's revenue (vs. 6% for the U.S.), highlighting geopolitical risks and America's lag in semiconductor manufacturing investments.
➂ Semiconductor equipment stocks (e.g., LRCX, ASML, AMAT) face profit-taking pressures due to AI-driven overvaluation and softening industry fundamentals.
June 30
- Jitter: The Overlooked PDN Quality Metric
➀ Jitter is identified as a critical yet underappreciated metric for evaluating PDN quality, particularly impacting DDR interfaces by limiting timing margins;
➁ A simulation methodology using 3D EM solvers and VHDL-AMS models is proposed to quantify PDN-induced jitter, enabling comparisons of decoupling capacitor configurations;
➂ Results reveal that flatter PDN impedance profiles outperform designs with lower impedance in reducing jitter, challenging traditional PDN optimization strategies.
April 1
- A Synopsys Webinar Detailing IP Requirements for Advanced AI Chips
➀ The webinar discusses the impact of generative AI on technology evolution and the rise in compute power demand.
➁ It covers the trends in larger compute chips, multi-die systems, advanced packaging, and memory architectures.
➂ Key technologies like die-to-die communication, custom HBMs, and 3D stacking are explored in detail.
- CEO Interview with Matthew Stephens of Impact Nano
➀ Matthew Stephens of Impact Nano has over 20 years of experience in advanced materials commercialization.
➁ Impact Nano is a tier 2 supplier specializing in advanced materials for semiconductor manufacturing.
➂ The company addresses challenges in materials innovation, scale-up, and manufacturing sustainability.
March 31
- An Important Advance in Analog Verification
➀ Mach42的发现平台利用机器学习创建一个代理模型，以实现更快的电路设计探索，而无需进行完整的SPICE模拟。
➁ 平台的目标是达到90%的准确率，允许快速迭代，同时保留在最终确认时进行完整准确性的选项。
➂ Mach42正在与Cadence合作开发Spectre，并计划开发Verilog-A模型，这可能会显著增强模拟-数字设计验证。
March 30
- Semiconductor CapEx Down in 2024 up in 2025
➀ Semiconductor capital expenditures (CapEx) are expected to decrease to $155 billion in 2024, before increasing to $160 billion in 2025.
➁ TSMC plans a significant increase in CapEx for 2025, estimating between $38 billion and $42 billion, while Micron Technology is projecting $14 billion.
➂ The CHIPS Act has allocated $32 billion in grants and $6 billion in loans to support semiconductor manufacturing in the U.S.
March 28
- CEO Interview with Dr Greg Law of Undo
➀ Undo's technology enables engineers to see exactly what their code did, facilitating root-cause analysis and improving collaboration.
➁ Undo is prominent in industries such as semiconductor design, databases, and networking, where debugging efficiency is critical.
➂ Undo's solution helps customers overcome challenges like development bottlenecks and missed deadlines by improving debugging processes.
- Upcoming Webinar: Accelerating Semiconductor Design with Generative AI and High-Level Abstraction
➀ Rise Design Automation has developed a solution that integrates generative AI with human expertise to improve RTL design productivity.
➁ The webinar hosted by RDA and SemiWiki will showcase how generative AI can enhance semiconductor design through high-level abstraction.
➂ The Rise AI solution translates natural-language intent into high-level design code, reducing manual effort in the design process.
March 27
- CEO Interview with Jonathan Klamkin of Aeluma
➀ Aeluma通过结合高性能材料和可扩展的硅制造技术，重新定义了半导体技术；
➁ Aeluma的技术在AI基础设施、国防、量子计算和下一代传感等领域产生了重大影响；
➂ Aeluma正在解决AI和高性能计算在扩展方面遇到的挑战，通过集成化合物半导体和大型衬底来实现大规模生产。
March 25
- Webinar: RF board design flow examples for co-simulating active circuits
➀ This webinar series focuses on 3D passive vendor component models for accurate EM-circuit co-simulation of high-frequency RF board designs.
➁ It explores simulating active circuits on boards using Modelithics models in Keysight EDA software.
➂ The Modelithics COMPLETE Library supports accurate simulations and provides a ready bill of materials.
- Ceva-XC21 and Ceva-XC23 DSPs: Advancing Wireless and Edge AI Processing
➀ Ceva recently unveiled the XC21 and XC23 DSP cores for advanced wireless and edge AI processing;
➁ The XC21 is optimized for low-power, high-performance applications in cost-sensitive markets;
➂ The XC23 provides significant performance improvements for high-end communications with AI capabilities.
- CEO Interview with Brad Booth of NLM Photonics
➀ Brad Booth, CEO of NLM Photonics, discusses his background in technology strategy.
➁ NLM Photonics aims to reduce power consumption in photonics by 50%.
➂ The company addresses the high power demands of AI data centers and focuses on energy-efficient modulation.
March 24
- Going Beyond DRC Clean with Calibre DE
➀ Achieving design rule compliance and optimal electrical performance in advanced semiconductor designs is crucial for minimizing design iterations and ensuring product reliability.
➁ Siemens Digital Industries Software's Calibre DesignEnhancer (DE) provides analysis-based EMIR solutions that enhance power integrity and reduce IR drop.
➂ Both Google and Intel utilized Calibre DE to address IR drop issues, demonstrating significant improvements in power grid robustness and electrical performance.
March 20
- Cut Defects, Not Yield: Outlier Detection with ML Precision
➀ Aggressive testing in chip manufacturing often leads to the discarding of marginally functional chips, causing waste.
➁ Traditional testing methods like PAT have limitations in detecting subtle defects.
➂ proteanTecs' outlier detection solution uses machine learning to enhance chip reliability and performance.
- 2025 Outlook with James Cannings QPT Limited
➀ QPT Limited致力于通过高频GaN电机驱动创新降低全球电力消耗5%；
➁ 2024年，与ABB合作开发了世界上首个1MHz GaN基7.5KW电机驱动；
➂ 预计2025年通过与ABB项目成果的战略合作伙伴关系，推动公司增长。
March 19
- Compute and Communications Perspectives on Automotive Trends
➀ Automotive electronics is advancing rapidly, focusing on autonomy, electrification, and car cockpit improvements.
➁ The need for advanced functionality is high, but OEMs aim to minimize costs and maximize software-driven features.
➂ Modern cars are equipped with multiple sensors, including cameras, radar, and lidar, requiring advanced fusion and processing techniques.
March 17
- How FD-SOI Powers the Future of AI in Automobiles
➀ The automotive industry is experiencing a revolution with the rise of software-defined vehicles and AI integration.
➁ Traditional ECU architectures are shifting towards centralized and zonal designs for efficiency and data handling.
➂ Soitec's FD-SOI technology is crucial for enhancing performance, energy efficiency, and reliability in next-generation automotive applications.
March 14
- CEO Interview with Fabrizio Del Maffeo of Axelera AI
➀ Axelera AI, founded in 2021, aims to provide scalable edge AI hardware and software solutions.
➁ The company has raised USD 120 million and has a world-class team of over 190 employees.
➂ Axelera AI's Metis platform offers high performance with low power consumption, targeting applications like computer vision, automotive, and healthcare.
- A Realistic Electron Blur Function Shape for EUV Resist Modeling
➀ The resolution in lithography is influenced by image blur in addition to wavelength and numerical aperture, which impacts image contrast and sensitivity to stochastic effects.
➁ Blur originates from various factors including flare, image fading, stage desynchronization, and electron behavior.
➂ Incorporating electron blur into lithography models is crucial for improving image resolution and reducing defectivity in advanced semiconductor manufacturing.
March 13
- Siemens Fleshes out More of their AI in Verification Story
➀ Siemens EDA在AI方面的深度，包括1400名AI专家和近4000项专利；
➁ 随着芯片复杂性的增加，行业预计到本世纪末将短缺27,000名专家设计师；
➂ Siemens利用三种类型的AI在验证领域：基于无监督学习的分析型AI、基于机器学习和统计分析的预测型AI，以及基于大型语言模型的生成/代理支持型AI。