➀ TSMC is expected to have the best 2nm process by the end of the year, with 60% yields on a GAA process in mass production in Q4 2025. ➁ Samsung is aiming for a Q4 launch for production on 2nm but won't optimize BSPD until 2027. ➃ Intel is also targeting a 2nm process with BSPD and GAA, despite 10% yields reported. ➄ Rapidus, a dark horse, is hoping to have its first 2nm prototype chips out this April with production by the end of the year and mass production in 2027.

➀ Rapidus has received an ASML EUV machine for installation at its IIM-1 foundry in Chitose, Hokkaido; ➁ This marks the first time EUV technology will be used for mass production in Japan; ➂ The TWINSCAN NXE:3800E machine can process 220 wafers an hour; ➃ Rapidus plans to start pilot silicon production at IIM-1 in April 2025 with a single-wafer process.

➀ Intel's initial promises under Pat Gelsinger were ambitious but execution has been lacking; ➁ The company faces challenges with a bloated workforce, risk-averse culture, and a lagging AI strategy; ➂ Intel's investments in process technology have not yielded significant results, and the company must make hard choices about its future.

➀ TSMC will start producing 2nm GAA-based wafers in Q4 2025 at Fab 20 in Hsinchu; ➁ The production will be followed by Fab 22 in Kaohsiung in Q1 2026; ➂ N2P production will start in late 2026 without backside power delivery; ➃ N2 and N2P will use TSMC's NanoFlex technology; ➄ N2 is 15% denser than N3E and improves performance by 10% to 15%; ➅ N2E will be followed by N2P and N2X in 2026; ➆ TSMC's planned capacity for 2nm is more than for 3nm; ➇ 2nm wafers are expected to cost $30k+.

➀ TSMC has won the FinFET race, with all major advanced logic designs, even Intel's, manufactured on its N5 and N3 processes in Taiwan. Competitors are falling behind. Samsung has performed poorly since 7nm, with low yields, and Intel is still in the early stages of its recovery with Intel 4 and Intel 3 nodes; major customers have not ordered these nodes in large quantities. ➁ The future of TSMC's dominance is uncertain. FinFET cannot be scaled further, and SRAM miniaturization has stalled for several nodes. The industry is at a critical turning point, and leading logic must adopt two new paradigms in the next 2-3 years: gate-all-around (GAA) and backside power delivery (BSPDN). ➂ Intel's failure at the 10nm node and the loss of 3 years of lead were due to many factors, including the failure to adopt EUV and transitioning to cobalt metallization with an immature tool supply chain despite warnings from Applied Materials that their tools were not ready. GAA and BSPDN bring new opportunities to the foundry competition and could even open the door to new entrants in the field such as Rapidus, a 2nm foundry startup supported by the Japanese government. ➃ As capital expenditures for building advanced wafer fabs soar, this could mean that Samsung or Intel may be forced out of the competition. The article delves into these themes, discussing BSPDN technology, the front-end logic roadmaps of all four fabs, the competitiveness of their process technologies, and SRAM scaling, among others.

➀ Intel has made a strong move after poor Q3 results, repositioning its foundry unit as an independent operation. This is aimed at attracting US rivals like AMD, Nvidia, and Qualcomm. The US Department of Commerce is encouraging this shift, with half of the world's top ten fabless companies based in the US. ➁ Intel's foundry unit is seen as a viable option for US hyperscalers looking for proprietary SOCs. ➂ With Intel's promise of the world's best foundry process next year, there's potential for significant growth.

➀ Intel's ability to catch up with TSMC in process technology is questioned; ➁ Malcolm Penn, CEO of Future Horizons, suggests it could take 10 years to catch up; ➂ Intel's process capability is about a year behind TSMC; ➃ TSMC has been running its 3nm process for a year, while Intel's best process in volume production is Intel 4 at Leixlip.

This week Samsung Electronics and Synopsys announced that Samsung has taped out its first mobile system-on-chip on Samsung Foundry's 3nm gate-all-around (GAA) process technology. The announcement, coming from electronic design automation Synopsys, further notes that Samsung used the Synopsys.ai EDA suite to place-n-route the layout and verify design of the SoC, which in turn enabled higher performance. Samsung's unnamed high-performance mobile SoC relies on 'flagship' general-purpose CPU and GPU architectures as well as various IP blocks from Synopsys. SoC designers used Synopsys.ai EDA software, including the Synopsys DSO.ai to fine-tune design and maximize yields as well as Synopsys Fusion Compiler RTL-to-GDSII solution to achieve higher performance, lower power, and optimize area (PPA). And while the news that Samsung has developed a high-performance SoC using the Synopsys.ai suite is important, there is another, even more important dimension to this announcement: this means that Samsung has finally taped out an advanced smartphone application processor on its cutting-edge 3nm GAAFET process. Although Samsung Foundry has been producing chips on its GAA-equipped SF3E (3 nm-class, 'early' node) process for almost two years now, Samsung Electronics has never used this technology for its own system-on-chips for smartphones or other complex devices. To date, SF3E has been used mainly for cryptocurrency mining chips, presumably due to the inevitable early teething and yield issues that come with being the industry's first commercial GAAFET process. For now, Samsung isn't disclosing what specific process node is being used for the SoC; the official Samsung/Synposys announcement only notes that it's for a GAA process node. Along with their first-generation 3nm-class SF3E, Samsung Foundry has a considerably more sophisticated SF3 manufacturing technology that offers numerous improvements over SF3E, and is due to be used for mass production in the coming quarters. Given th

As part of Samsung's Q1 earnings announcement, the company has outlined some of its foundry unit's key plans for the rest of the year. The company has confirmed that it remains on track to meeting its goal of starting mass production of chips on its SF3 (3 nm-class, 2nd Generation) technology in the second half of the year. Meanwhile in June, Samsung Foundry will formally unveil its SF2 (2 nm-class) process technology, which will offer a mix of performance and efficiency enhancements. Finally, the company the company is preparing a variation of its 4 nm-class technology for integration into stacked 3D designs. SF2 To Be Unveiled In June Samsung plans to disclose key details about its SF2 fabrication technology at the VLSI Symposium 2024 on June 19. This will be the company's second major process node based upon gate-all-around (GAA) multi-bridge channel field-effect transistors (MBCFET). Improving over its predecessor, SF2 will feature a 'unique epitaxial and integration process,' which will give the process node higher performance and lower leakage than traditional FinFET-based nodes (though Samsung isn't disclosing the specific node they're comparing it to). Samsung says that SF2 increases performance of narrow transistors by 29% for N-type and 46% for P-type, and wide transistors by 11% and 23% respectively. Moreover, it reduces transistor global variation by 26% compared to FinFET technology, and cuts product leakage by approximately 50%. This process also sets the stage for future advancements in technology through enhanced design technology co-optimization (DTCO) collaboration with its customers. One thing that Samsung has not mentioned in context of SF2 is backside power delivery, so at least for the moment, there is no indication that Samsung will be adopting this next-gen power routing feature for SF2. Samsung says that the design infrastructure for SF2 – the PDK, EDA tools, and licensed IP – will be finalized in the second quarter of 2024. Once this happe