➀ TSMC has won the FinFET race, with all major advanced logic designs, even Intel's, manufactured on its N5 and N3 processes in Taiwan. Competitors are falling behind. Samsung has performed poorly since 7nm, with low yields, and Intel is still in the early stages of its recovery with Intel 4 and Intel 3 nodes; major customers have not ordered these nodes in large quantities. ➁ The future of TSMC's dominance is uncertain. FinFET cannot be scaled further, and SRAM miniaturization has stalled for several nodes. The industry is at a critical turning point, and leading logic must adopt two new paradigms in the next 2-3 years: gate-all-around (GAA) and backside power delivery (BSPDN). ➂ Intel's failure at the 10nm node and the loss of 3 years of lead were due to many factors, including the failure to adopt EUV and transitioning to cobalt metallization with an immature tool supply chain despite warnings from Applied Materials that their tools were not ready. GAA and BSPDN bring new opportunities to the foundry competition and could even open the door to new entrants in the field such as Rapidus, a 2nm foundry startup supported by the Japanese government. ➃ As capital expenditures for building advanced wafer fabs soar, this could mean that Samsung or Intel may be forced out of the competition. The article delves into these themes, discussing BSPDN technology, the front-end logic roadmaps of all four fabs, the competitiveness of their process technologies, and SRAM scaling, among others.