<p>➀ Silicon Creations' low-area PLL technology integrates with Codasip's test chip for evaluating L31AS dual-core CPU and crypto accelerator; </p><p>➁ Collaboration advances automotive safety-critical systems using RISC-V cores and analog IP; </p><p>➂ PLL's compact design addresses space-sensitive automotive applications while ensuring reliability</p>
Related Articles
- RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint5 days ago
- SiFive 2nd Gen Intelligence Family Launchedabout 1 month ago
- S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China2 months ago
- What XiangShan Got Right—And What It Didn’t Dare Try2 months ago
- Unlocking Efficiency and Performance with Simultaneous Multi-Threading2 months ago
- Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm3 months ago
- Codasip platform accelerates CHERI adoption6 months ago
- Over 250 billion Arm chips have shipped since the first ARM1 processor launched 40 years ago6 months ago
- 2D 32-bit RISC-V processor6 months ago
- Embracing Multicore and RISC-V Architectures in SoC Design7 months ago