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September 24
- Semiconductor Equipment Spending Healthy
➀ Global semiconductor equipment spending surged 23% YoY in Q2 2025, reaching $33.07B, with China ($11.36B), Taiwan ($8.77B), and South Korea leading regional investments.
➁ North America’s spending declined due to wafer fab delays (Intel, Micron, Samsung) amid administration policy shifts, while TSMC drove Taiwan’s 125% growth through aggressive CapEx.
➂ 2025 global CapEx is projected at $160B (+3% YoY), but 2026 forecasts vary; concerns grow over U.S. CHIPS Act implementation under Trump’s equity-focused strategy.
- Yuning Liang’s Painstaking Push to Make the RISC-V PC a Reality
➀ Yuning Liang, founder of DeepComputing, pioneered a modular RISC-V laptop design enabling component upgrades, driven by his software-to-hardware career shift and partnerships with companies like Framework.
➁ The project faced technical and geopolitical motivations, leveraging RISC-V to bypass chip trade restrictions and fostering open-source hardware collaboration, though early prototypes like the $5,000 Roma laptop faced financial challenges.
➂ Key hurdles include software ecosystem gaps (e.g., Chromium’s lack of native RISC-V support) and scaling efforts through community-driven initiatives like RISE to integrate RISC-V into mainstream infrastructure.
- Arm Lumex Pushes Further into Standalone GenAI on Mobile
➀ Arm introduces Lumex platform for on-device GenAI on mobile, emphasizing CPU clusters over GPU/NPU;
➁ On-device AI addresses cloud dependency issues (latency, security, privacy) and offers real-time interactions;
➂ Lumex's SME2 technology and CPU-centric design deliver up to 5X performance gains and simplified developer workflows
September 23
- Soitec’s “Engineering the Future” Event at Semicon West 2025
➀ Soitec will host an exclusive event titled 'Engineering the Future' at Semicon West 2025, focusing on how its engineered substrates address challenges in 5G/6G, AI, and data centers;
➁ The agenda includes executive insights, deep dives into RF technologies for smartphones, optical interconnects, and edge AI devices, with participation from industry leaders like Qualcomm and IBM;
➂ The event highlights Soitec’s role in enabling sustainable innovation through substrates like SOI and strained silicon, crucial for next-gen semiconductor advancements.
- The Impact of AI on Semiconductor Startups
➀ AI is revolutionizing chip design by reducing development time by up to 40% through cloud-based EDA tools and automated verification processes, enabling startups to compete with industry giants;
➁ The semiconductor industry faces a critical talent shortage (projected 1M skilled workers deficit by 2030) that threatens innovation, while cloud infrastructure emerges as a democratizing force providing equitable access to cutting-edge design resources;
➂ Despite AI's transformative impact, human expertise remains irreplaceable in architectural innovation, with the future vision pointing towards "Chip as a Service" models that could compress development cycles from years to months.
September 22
- MediaTek Dimensity 9500 Unleashes Best-in-Class Performance, AI Experiences, and Power Efficiency for the Next Generation of Mobile Devices
➀ MediaTek Dimensity 9500, built on TSMC's N3P process, features a third-gen All Big Core CPU architecture with a 4.21GHz ultra core, delivering 32% and 17% boosts in single/multi-core performance while reducing power consumption by 55% at peak loads.
➁ The chip integrates a ninth-gen NPU 990 with Generative AI Engine 2.0, enabling BitNet 1.58-bit large model processing and 4K image generation, while reducing AI power usage by 25%-56% for real-time user personalization.
➂ Enhanced gaming features include an Arm G1-Ultra GPU (33% faster peak performance), 120FPS frame interpolation, Unreal Engine 5.6 ray tracing, and advanced imaging via Imagiq 1190 ISP supporting 200MP capture and 4K 60FPS portrait video.
September 21
- CEO Interview with Barun Kar of Upscale AI
➀ Barun Kar, CEO of Upscale AI, discusses the company's focus on developing open-standard, full-stack solutions for AI networking infrastructure to address ultra-low latency and scalability challenges；
➁ Upscale AI differentiates itself by prioritizing interoperability and flexibility, moving away from proprietary systems through technologies like UALink and SONiC；
➂ The company recently secured $100 million in seed funding, aiming to democratize AI network infrastructure for hyperscalers and neocloud providers.
September 19
- CEO Interview with Adam Khan of Diamond Quanta
➀ Diamond Quanta is commercializing engineered diamond semiconductors, achieving n- and p-type doping through proprietary methods to surpass the thermal and electrical limits of SiC and GaN;
➁ Their platform targets high-performance applications in power electronics, quantum photonics, and extreme-environment sensors, delivering up to 50% system cooling reduction and 70% BOM savings;
➂ Collaborating with industry leaders and Silicon Catalyst, the company aims to scale production and validate diamond's role in next-gen electronics, optics, and quantum technologies.
September 18
- SiFive Launches Second-Generation Intelligence Family of RISC-V Cores
➀ SiFive launches second-generation RISC-V Intelligence cores (X100/X200/X300/XM) for edge to data center AI workloads, emphasizing high performance and low power consumption;
➁ The X-Series cores function as standalone AI inference processors or accelerator control units, outperforming Arm's Cortex-M85 by up to 230% in MLPerf Tiny benchmarks;
➂ Innovations include hardware exponential acceleration, enhanced memory architecture, and a complete AI software stack supporting TensorFlow/PyTorch integration.
September 16
- MediaTek Develops Chip Utilizing TSMC’s 2nm Process, Achieving Milestones in Performance and Power Efficiency
➀ MediaTek has developed its first 2nm chip using TSMC's nanosheet transistor technology, with mass production set for late 2026;
➁ The 2nm process achieves 18% performance gain, 36% power reduction, and 1.2x logic density improvement over 3nm technology;
➂ This collaboration strengthens MediaTek's leadership in AI, 5G/6G, and smart devices while shaping next-gen automotive and HPC solutions
September 15
- Something New in Analog Test Automation
➀ Siemens introduces Tessent AnalogTest, a novel EDA tool automating analog testing in SoCs using digital scan-based methods and evolving IEEE standards (P2427, P1687.2).
➀ The solution reduces analog defect simulation times from days to minutes, integrates IJTAG for test access, and achieves 10X-100X faster test times while maintaining coverage comparable to traditional methods.
➁ By supporting ISO 26262 functional safety metrics and standardized defect modeling, the technology particularly benefits automotive applications needing high-reliability verification.
- Advancing Semiconductor Design: Intel’s Foveros 2.5D Packaging Technology
➀ Intel's Foveros 2.5D uses 3D die stacking with a 36μm microbump pitch for high-density chiplet integration;
➁ The technology reduces latency by 50% vs traditional packaging and aligns with UCIe for multi-vendor interoperability;
➂ Variants like Foveros-S/R/B enable tailored solutions from HPC to cost-sensitive IoT applications
September 12
- Synopsys Announces Expanding AI Capabilities and EDA AI Leadership
➀ Synopsys.ai Copilot utilizes generative AI to address semiconductor design complexity and workforce shortages, reducing documentation searches by 30% and enabling 20x faster script generation.
➁ Integration with Ansys and partnerships with Microsoft/NVIDIA enhance multi-physics simulation capabilities and cloud scalability, supporting advanced 3D IC and SoC designs.
➂ Early adopters like Intel and AMD report 35% productivity gains, while upcoming autonomous workflow tools like 3DSO.ai aim to revolutionize chip design efficiency.
September 11
- Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICs
➀ ECO (Engineering Change Order) is crucial for post-layout modifications in mixed-signal ASIC designs, addressing challenges from analog-digital interactions;
➁ Richard Chang's webinar explores three key drivers of ECO requirements and demonstrates Easylogic's automated solutions to reduce turnaround time and design complexity;
➂ The session provides practical insights on RTL-based tracing and seamless integration for tapeout success.
- The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)
➀ In-Circuit Emulation (ICE) emerged as a breakthrough in semiconductor verification, enabling 1,000x faster testing than traditional HDL simulations through FPGA-based hardware platforms;
➁ Early ICE faced limitations with rigid speed adapters and non-deterministic debugging, prompting a shift to virtual transaction-based verification by the 2000s for improved flexibility and software co-verification;
➂ Modern 3rd-gen speed adapters integrate real PHY layers, 100Gbps bandwidth, and multi-user deployment, bridging functional and system-level validation for complex SoCs.
September 10
- Tessent MemoryBIST Expands to Include NVRAM
➀ Siemens' Tessent MemoryBIST now supports NVRAM testing with configurable controllers and hierarchical BIST architecture;
➁ The solution addresses emerging challenges in 3D IC designs and advanced process nodes through automated trimming/calibration workflows;
➂ Enables field-repairable memory systems with integrated ECC and multi-level test capabilities for AI-driven applications.
- The Importance of Productizing AI. Everyday Examples
➀ The author highlights challenges in AI productization through personal experiences with image generation anomalies and voice command limitations in car infotainment systems;
➁ AI systems (DALL-E 3, Siri) demonstrate unpredictable 'hallucinations' and ambiguous interaction boundaries that impair user productivity/safety;
➂ Proposed solutions include implementing validation layers, clearer capability signaling, and user education to align expectations with AI's actual limitations.
September 9
- Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet
➀ Backed by the Japanese government and IBM, Rapidus aims to achieve 2nm chip production by 2027, challenging TSMC's dominance in advanced semiconductor manufacturing;
➁ The company is adopting a high-risk strategy of upfront payments to IP vendors to bypass ecosystem challenges, diverging from TSMC's royalty-based model;
➂ While achieving technical milestones with IBM's assistance, concerns persist about financial sustainability and replicating TSMC's ecosystem advantages like talent pipelines and co-location benefits.
- Exploring Cycuity’s Radix-ST: Revolutionizing Semiconductor Security
➀ Cycuity's Radix-ST uses static analysis to detect hardware vulnerabilities at the RTL design phase, reducing late-stage security risks;
➁ The tool integrates with MITRE's CWE database, offering actionable insights and complementing dynamic verification methods;
➂ It addresses chip security gaps in industries like automotive and defense, aligning with 'secure by design' principles amid rising cyber threats.
September 8
- Smart Verification for Complex UCIe Multi-Die Architectures
➀ Multi-die architectures using UCIe protocol face verification challenges including inter-die communication and evolving protocol features;
➁ Siemens EDA's Questa One Avery™ VIP provides layered verification with AI-driven coverage and configurable testbenches;
➂ The solution supports compliance testing, real-time performance monitoring, and scalability from simulation to hardware prototyping.
- PDF Solutions Adds Security and Scalability to Manufacturing and Test
➀ Semiconductor manufacturing faces escalating challenges due to 3D IC complexity and global supply chain demands, with PDF Solutions addressing these through advanced data platforms;
➁ PDF introduces Exensio® Analytics Platform and DEX to enable real-time data collection & AI-driven test optimization, reducing costs while improving yield and reliability;
➂ The Data Feed Forward (DFF) framework utilizes upstream test data to dynamically adjust downstream testing strategies, marking a shift toward AI-driven manufacturing ecosystems.
September 7
- Revolutionizing Processor Design: Intel’s Software Defined Super Cores
➀ Intel's SDC patent introduces virtual core fusion via software-hardware co-design to boost single-thread performance without physical scaling;
➀ The technology splits workloads across multiple cores using 'wormhole addresses' for parallel execution while maintaining program order;
➂ SDC enhances energy efficiency by 20-30% and enables dynamic reconfiguration between single/multi-thread modes, reducing reliance on advanced process nodes.
- TSMC’s 2024 Sustainability Report: Pioneering a Greener Semiconductor Future
➀ TSMC released its 2024 Sustainability Report, committing to net zero by 2050 and achieving 104.2 billion kWh energy savings in 2024 (reducing 44 million tons of CO₂);
➁ Environmental initiatives include 60% renewable energy by 2030, water stewardship goals, and a supplier carbon reduction program targeting Scope 3 emissions;
➂ Social efforts feature workplace equity (40% women workforce), NT$2.44B social investments, and governance milestones with NT$2.95T revenue (69% from cutting-edge 7nm processes).
- Intel’s Commitment to Corporate Responsibility: Driving Innovation and Sustainability
➀ Intel's 2024-25 Corporate Responsibility Report outlines a revamped strategy under CEO Lip-Bu Tan, integrating transparency, ethics, and human rights while aligning with UN Sustainable Development Goals.
➁ Environmental milestones include achieving 98% global renewable electricity, 24% reduction in Scope 1/2 emissions since 2019, and a net-zero target by 2040, alongside water stewardship and circular economy practices.
➂ Technology-driven initiatives focus on AI skills training for 8 million people, 465 global social impact projects, and improved product energy efficiency while advancing responsible AI governance.
September 5
- TSMC 2025 Update: Riding the AI Wave Amid Global Expansion
➀ TSMC dominates 2nm/3nm foundry with over 90% market share, achieving $60.5B H1 2025 revenue;
➁ 2nm HVM to start in Q4 2025 with early yield success;
➂ Global expansion includes profitable Arizona fab and 1.4nm R&D under Taiwan's tech protection laws
September 1
- Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUs
➀ High-performance CPU design is transitioning from traditional Out-of-Order (OOO) architectures to Time-Based OOO, leveraging RISC-V's open ecosystem to improve power efficiency and scalability.
➁ Condor Computing's Cuzco processor uses a slice-based microarchitecture and predictive scheduling via a Time Resource Matrix, enabling flexible configurations for datacenter, mobile, and automotive applications.
➂ Key advantages include superior performance-per-watt, simplified verification, and ISA extensibility, positioning RISC-V as a competitive alternative to legacy architectures like x86 and ARM.
- Orchestrating IC verification: Harmonize complexity for faster time-to-market
➀ Modern IC verification complexity demands orchestrated workflow systems akin to conducting an orchestra, enabling unified management of tasks across tools and teams;
➁ Fragmented verification processes lead to inefficiencies such as manual errors and resource bottlenecks, while orchestration systems provide automation, intelligent resource allocation, and centralized monitoring;
➂ Siemens' Calibre MJS exemplifies this approach, reducing runtime by 30%-50% and improving design iteration efficiency through features like single-layout streaming and license optimization.
August 31
- Basilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status Quo
➀ Basilisk is a groundbreaking RISC-V SoC developed with fully open-source EDA tools, demonstrating Linux capability on industrial-grade silicon via mature 130nm BiCMOS process；
➁ The project challenges traditional IP/EDA business models, highlighting U.S. incumbents' innovation stagnation versus rapid progress in Europe and China pursuing sovereign chip ecosystems；
➂ Open-source tools like Yosys and OpenROAD achieved silicon success with 64-102MHz operation, GPU-like voltage scalability, and energy efficiency optimization, enabling next-gen 22nm FD-SOI designs
- CEO Interview with Nir Minerbi of Classiq
➀ Classiq is a quantum software startup specializing in automated quantum algorithm design, allowing users to focus on functional requirements rather than manual gate-level coding;
➁ The company targets enterprise applications in finance, pharmaceuticals, automotive, and aerospace, addressing challenges like portfolio optimization and molecular simulations;
➂ Classiq differentiates through its high-level modeling language (Qmod) and patented synthesis engine, achieving up to 97% quantum circuit compression while supporting multi-platform deployments.
August 29
- GlobalFoundries 2025 Update GTS25
➀ GlobalFoundries (GF) has solidified its role as a leading contract semiconductor manufacturer, focusing on automotive, IoT, and autonomous systems with mature technologies like FD-SOI and FinFET.
➁ GF reported strong Q2 2025 revenue of $1.688 billion, driven by strategic partnerships and acquisitions, including MIPS Technologies to expand RISC-V IP for AI applications.
➂ Despite market volatility and geopolitical risks, GF emphasizes sustainability and regional strategies (e.g., 'China-for-China') to secure its position as the third-largest pure-play foundry globally.