➀ Ex-Intel CEO Pat Gelsinger advises Japan's Rapidus to develop unique differentiating technologies beyond production efficiency to compete with TSMC.

➁ Rapidus plans to integrate wafer fabrication and advanced packaging at the same facility for faster cycles, though full automation will not be available immediately from 2027.

➂ The company aims to begin 2nm test production with GAA transistors and establish a chiplets R&D center, utilizing ASML EUV lithography tools for future HBM and 3D packaging.

➀ Counterpoint Research's analysis defines Foundry 2.0 as encompassing packaging and mask-making alongside wafer fabrication, with TSMC leading at 35% market share and Intel ranking second at 6.5%;

➁ The expanded definition may mitigate monopoly concerns for TSMC, whose traditional wafer fabbing dominance reaches nearly 70%;

➂ The Foundry 2.0 market reached $72 billion in Q1 2025, with Intel gaining 0.6% quarterly market share but declining 0.3% year-over-year.

➀ TSMC's 2nm process yield surpasses 60%, meeting HVM requirements for stable production;

➁ Samsung's 2nm yield lags at 40%, prompting major clients like AMD, Nvidia, and Apple to prioritize TSMC capacity;

➂ TSMC's 2nm wafer price approaches $30,000, with future 1.4nm costs projected to reach $45,000 by 2028.

➀ Tesla developed a groundbreaking 'Stress' tool to detect defective cores in its wafer-scale Dojo processors, critical for preventing silent data corruption that could invalidate weeks of AI training;

➁ Each Dojo 'Training Tile' contains 8,850 RISC-V cores and leverages TSMC's InFO_SoW packaging, with Stress enabling real-time monitoring across millions of cores without downtime;

➂ The method not only identifies faulty cores but also exposed rare design flaws, positioning Tesla alongside Google and Meta in hardware reliability while shaping future wafer-scale chip adoption.