➀ Intel is facing a major talent exodus with high-level employees leaving the company rapidly; ➁ Habana Labs co-founders David Dahan and Ran Halutz have left Intel to start an AI startup named Touch; ➂ Four senior CPU engineers from Intel have also left to found a new RISC-V core IP development company named Ahead Computing Inc.

➀ The popularity of RISC-V is rising, with industry giants like Intel, STMicroelectronics, and others investing in RISC-V startups; ➁ RISC-V is seen as a foundational technology for the digital infrastructure of the AI era, offering simplicity, openness, flexibility, low power consumption, modularity, and scalability; ➂ RISC-V is expected to become the native computing architecture for the AI era, with a significant market opportunity in the digital infrastructure sector.

➀ Nee Guohua emphasized that the integration of RISC-V and Chiplet will promote the innovation of DSA (Domain Specific Architecture) and lead to the 'Hardware Defined by Demand' era; ➁ The level of China's chip design has reached the world's advanced level in digital chips, but there is still a gap in analog chips; ➂ Scientists must not only have solid professional knowledge but also be brave in innovation and willing to take responsibility; ➃ RISC-V, as an emerging open instruction set architecture, is gaining global attention and is expected to promote innovation with its openness, efficiency, flexibility, low power consumption, modularity, and scalability; ➄ Chiplet technology, which encapsulates multiple pre-designed small chips into a complete SoC, is introduced to lower design complexity and cost while improving performance and flexibility; ➅ DSA (Domain Specific Architecture) computing architecture, characterized by customized design to better meet specific needs, shows great potential in emerging fields such as AI and IoT; ➆ The integration of RISC-V, extended instruction sets, Chiplet, and interconnect technologies in DSA new servers is expected to replace traditional X86 servers in terms of cost-performance and energy consumption, thus promoting the transformation and development of the Chinese server market; ➇ In the new era of 'Hardware Defined by Demand', hardware design will no longer rely solely on traditional standardized and generalized approaches but will be more closely integrated with actual application needs.

➀ The Orange Pi RV is a single-board computer featuring a RISC-V processor, making it one of the first in the Orange Pi lineup to adopt this architecture. ➁ It measures 89 x 56mm and is powered by a 1.5 GHz StarFive JH7110 processor with up to 8GB of LPDDR4-2800 memory. ➂ The board includes a variety of ports and connectors such as 4 USB 3.0, 1 USB 2.0 Type-C, HDMI, and Gigabit Ethernet, along with support for WiFi 5 and Bluetooth 5.

➀ ST has joined Quintauris, a RISC-V facilitator, as its sixth shareholder. ➁ Quintauris aims to advance the adoption of RISC-V-based products. ➂ Initial applications will focus on the automotive sector, with plans to expand to mobile and IoT.

➀ Four senior Intel CPU experts have left to form a RISC-V startup called AheadComputing. ➁ The team, with over 80 years of combined experience at Intel, aims to develop open specification core IP. ➂ AheadComputing could be an attractive acquisition target for companies like AMD.

➀ SiFive and PQShield have partnered to integrate post-quantum cryptography into SiFive’s high-performance processor families. ➁ This collaboration aims to protect critical systems from quantum attacks and accelerate the adoption of NIST's post-quantum cryptography standards on RISC-V technologies. ➂ The integration of PQShield’s PQPlatform-CoPro technology with SiFive’s processors ensures quantum-resistant hardware security and compliance with NIST standards without compromising performance.

➀ Jesse Taube has successfully ported RISC-V NOMMU Linux to the RP2350, a Raspberry Pi variant. ➁ The code is available on GitHub for use on the SparkFun Pro Micro – RP2350. ➂ This development opens up new possibilities for running Linux on RISC-V-based microcontrollers.

➀ RISC-V architecture manages to run The Witcher 3 at 15 FPS using emulation layers. ➁ The achievement is significant for the future of open-source architecture in gaming. ➂ Challenges remain in translating x86 instructions to RISC-V, affecting performance.

➀ The Witcher 3 becomes the first AAA game to run on an RISC-V machine using Box64, Wine, and DXVK. ➁ Challenges included limited OpenGL support and the need for more x86 instructions in RISC-V. ➂ Progress was made with the introduction of devices like the Milk-V Pioneer and the SpacemiT K1/M1 SoC, which support RISC-V Vector Extension (RVV). ➃ RISC-V still lacks certain critical instructions for efficient x86 emulation compared to other architectures. ➄ Despite limitations, The Witcher 3 runs at up to 15 fps in-game and full speed on the main menu on RISC-V hardware.

➀ Tenstorrent unveiled its Blackhole silicon at Hot Chips 2024, featuring a standalone AI computer based on Ethernet. ➁ The Blackhole chip includes sixteen RISC-V cores in four clusters, with additional 'baby' RISC-V cores for compute, data movement, and storage. ➂ It supports 10x 400Gbps Ethernet and 512GB/s of bandwidth, emphasizing data locality and minimizing off-chip DRAM usage. ➃ The architecture leverages Ethernet for scaling, avoiding the need for specialized interconnects like NVLink or InfiniBand. ➄ TT-Metalium is introduced as part of the low-level programming model to facilitate AI operations on the hardware.

➀ DeepComputing introduces the DC-ROMA RISC-V Pad II, a tablet powered by a RISC-V 64-bit 8-core CPU. ➁ The device supports Ubuntu 24.04 and Android 15, with options for up to 16GB RAM and 128GB storage. ➂ This tablet aims to facilitate mobile app development for the RISC-V architecture, especially beneficial for Chinese companies facing U.S. hardware restrictions.

➀ Four senior CPU architects from Intel, with a combined experience of over 80 years, have founded AheadComputing, a RISC-V technology startup. ➁ The founders, Debbie Marr, Mark Dechene, Jonathan Pearce, and Srikanth Srinivasan, have extensive experience in CPU architecture and microarchitecture. ➂ AheadComputing aims to develop attractive open-specification core IP and is currently recruiting talent with CPU design and verification experience.

➀ Akeana, backed by top investors, officially launches with a range of customizable RISC-V IP solutions. ➁ The company introduces three processor lines and SoC IP, ready for customer delivery. ➂ Akeana also offers an AI Matrix computation engine designed for AI acceleration.

➀ Synopsys will host the IP Processor Summit 2024 in Santa Clara, focusing on RISC-V solutions for IoT and automotive applications. ➁ The keynote speaker, Alexander Kocher, CEO of Quantauris, will discuss the benefits and challenges of RISC-V adoption. ➂ The event will provide in-depth information on ARC-V™ RISC-V processor IP and other related technologies.

➀ Introduces the CC2560A, the world's first RISC-V core super SIM chip, designed for multi-interface, high-security, and large-capacity smart card applications. ➁ Features a 32-bit RISC-V embedded security processor with a 120MHz clock speed, significantly enhancing transmission rates and computational power. ➂ Emphasizes advanced security measures including hardware-level encryption, EAL5+ certification, and support for international and national cryptographic algorithms.

➀ The Raspberry Pi Pico 2 features a price increase from $4 to $5, but offers enhanced functionalities including support for two processor architectures. ➁ The device maintains the same dimensions and GPIO configurations as its predecessor, with the microcontroller chip upgraded from RP2040 to RP2350 series, ensuring software and hardware compatibility. ➂ The RP2350 series microcontroller includes two Arm Cortex-M33 and two 32-bit Hazard3 RISC-V cores, allowing users to select which cores to use during the boot process.

➀ RISC-V's flexibility and scalability make it an ideal choice for AI chip design, allowing customization of AI accelerators. ➁ Two main models of RISC-V AI chips are identified: Integrated mode for low power and Attached mode for high computational power. ➂ Challenges in the RISC-V+AI ecosystem include fragmentation and insufficient resources, addressed through international standards and open-source software. ➃ Focus on edge computing and smart terminals to build a competitive software ecosystem against NVIDIA's CUDA. ➄ International collaboration and open-source community development are crucial for RISC-V's global market positioning.

➀ The Raspberry Pi Pico 2 features dual RISC-V Hazard3 cores, alongside Arm Cortex-M33 cores, selectable at boot time. ➁ It includes enhanced security features such as Arm TrustZone, signed boot, and hardware TRNG. ➂ The board supports both FreeRTOS and Zephyr operating systems, expanding its application possibilities.

➀ Raspberry Pi has introduced RISC-V cores on its new microcontroller, alongside Arm Cortex-M33 cores, making RISC-V more accessible. ➁ The new microcontroller, Proc0 and Proc1, can be independently set to either Arm Cortex-M33 or RISC-V core at boot. ➂ Raspberry Pi has also launched the Pico 2 development/application board to support the MCU, with additional boards featuring Wi-Fi, Bluetooth, or LoRa announced by other companies.