1. TSMC is reportedly planning to increase the prices for its N3 production and packaging by up to 20%. 2. This price hike is expected to coincide with the ramp-up of next-generation products from Nvidia and Intel. 3. The increase in quotes has been suggested by analysts and reported by media sources.

1. Intel's Lunar Lake processors, featuring the Core Ultra V200, have entered mass production at TSMC. 2. The Compute-Tile, including P- and E-cores, GPU, NPU, and Side Cache, is manufactured using TSMC's N3B process. 3. The Platform-Controller-Tile is also produced by TSMC using the N6 process, while the Base-Tile is from Intel. 4. The integrated Foveros packaging and final assembly of the Lunar Lake processors are completed at TSMC.

1. TSMC has temporarily halted the construction of its CoWoS (Chip on Wafer on Substrate) fabrication facility. 2. The suspension is due to the unexpected discovery of archaeological ruins at the construction site. 3. This delay impacts TSMC's plans for expanding its advanced packaging capabilities.

1. TSMC's construction of its new CoWoS advanced packaging plant in Chiayi, Taiwan was halted this month after archaeological ruins were discovered. 2. TSMC has proposed a plan to build a second CoWoS advanced packaging facility in the Southern Science Park Administration of the National Science and Technology Council. 3. A cultural review meeting has been convened, and it was resolved that construction process will be monitored daily, regardless of whether it's a sensitive area or not.

1. TSMC's Technology Symposium highlights the company's advanced technology and its ecosystem, focusing on advanced packaging solutions. 2. Advanced packaging has evolved from a simple finishing step to a critical part of the design process, driven by the need for heterogeneous integration of multiple dies. 3. TSMC's 3DFabric™ Technology Portfolio includes CoWoS®, InFO, and TSMC-SoIC®, which support multi-chip packaging and 3D IC stacking, enhancing system performance and functionality.

1、恩普 Tây 和 Vanguard 将建立一个名为 VisionPower Semiconductor Manufacturing Company Pte Ltd（VSMC）的合资企业，并在新加坡建立一个新的 300mm 半导体wafer 制造工厂。 2、本工厂将支持 130nm 到 40nm 的混合信号、电源管理和模拟产品，目标是汽车、工业、消费和移动端市场。 3、该合资企业将创建约 1,500 个工作岗位，并计划在 2027 年开始生产。

1、TSMC的3D堆叠SoIC包装技术正在快速发展，计划2027年达到3μm间距。 2、TSMC的SoIC-X技术将在2027年实现A16和N2两代芯片的堆叠。 3、TSMC还将推出两种新的.packaging技术：SoIC-X和SoIC-P，适用于不同性能和 APPLICATION场景。

1、中国刚刚设立了一个47.5亿美元的基金，以支持其 نیم自主芯片生产。 2、这被视为对美国出口控制的反应。 3、分析师认为，尽管中国有才华的工程师和政府支持，但制造最先进的芯片仍然是一个艰难的挑战。

1、台积电将在2025年推出N3X和N2P两种工艺技术，前者关注极致性能，后者关注能效和密度。 2、N3X相比N3P，可以降低7%的功耗或提高5%的性能。 3、N2P和A16将于2026年推出，前者是高性能版，后者是1.6nm级别的工艺技术，具备后端电源网络。

1、TSMC将扩展CoWoS存储容量，Compound Annual Growth Rate（CAGR）为60%，以满足日益增长的需求。 2、到2026年，CoWoS存储容量将增加四倍。 3、TSMC还将扩展SoIC 3D堆叠技术的容量，Compound Annual Growth Rate（CAGR）为100%。

1、Asicland获得AI公司D.notitia的订单，价值9.7亿元韩元。 2、D.notitia将使用Asicland设计的SoC来运行其大型语言模型（LLM）。 3、Asicland还与另一个韩国AI公司签订了价值10亿元的订单。

1、TSMC 是 EUV lithography 的领导者，拥有最多的 EUV 工具安装基础。 2、TSMC 的 EUV 晶圆生产能力已经从 2019 年的 1 倍增加到 30 倍。 3、TSMC 通过在 pellicle技术上的创新，提高了 EUV reticles 的使用寿命和输出能力。

1、台積電计划扩展其特色技术生产能力，到2027年增长50%。 2、该公司将推出新的4nm N4e低功率生产节点，用于各种应用。 3、台積電预计未来四到五年内将其特色生产能力扩大到1.5倍。

1、TSMC 将生产基于 12nm 和 5nm 节点的下一代 HBM4 基底_die。 2、该公司正在与 Micron、Samsung 和 SK Hynix 等 MEMORY 厂商合作，使用高级逻辑 process 制作 HBM4 基底_die。 3、HBM4 基底_die 将采用 N12FFC+ 和 N5 两种制程技术，提供更高的性能和更低的功耗

1、TSMC将在2024年下半年开始大量生产N3P工艺，提高性能效率和transistor密度。2、N3E工艺已经实现大量生产，yield性能优良。3、N3P工艺是N3E的光学缩小版，具有更高的性能效率和transistor密度。

The recent TSMC Technology Symposium in the Bay Area showcased the company’s leadership in areas such as solution platforms, advanced and specialty technologies, 3D enablement and manufacturing excellence. As always, the TSMC ecosystem was an important part of the story as well and that topic is the subject of this post. Analog… Read More The post Analog Bits Continues to Dominate Mixed Signal IP at the TSMC Technology Symposium appeared first on SemiWiki.

SK Hynix is planning to use TSMC’s base die technology for its next-generation high bandwidth memory (HBM).