08/25/2024, 07:50 PM UTC
UCIe 2.0：通用Chiplet互连快速架构简介UCIe 2.0: An Overview of the Universal Chiplet Interconnect Express Architecture
➀ UCIe是一种开放的、支持多协议的封装内互连标准，用于连接同一封装上的多个芯片，旨在支持分解式芯片架构的充满活力的生态系统。➁ 它支持多种协议，包括PCIe、CXL和Streaming，并允许映射任何选择的协议，只要两端都支持。➂ UCIe包含SoC构建所需的元素和与封装相关的外形尺寸，如凸块位置和散热解决方案。➃ UCIe可管理性架构为基于UCIe的系统级封装（SiP）提供标准化测试和调试基础设施。➄ UCIe支持三种封装选项：标准封装（2D）、高级封装（2.5D）和UCIe-3D，涵盖从最低成本到最佳性能互连的范围。➀ UCIe is an open, multi-protocol interconnect standard for connecting multiple chips within the same package, aiming to support a vibrant ecosystem for disaggregated chip architectures. ➁ It supports various protocols including PCIe, CXL, and Streaming, and allows for the mapping of any chosen protocol as long as both ends support it. ➂ UCIe includes elements necessary for SoC construction and package-related features such as bump placement and thermal solutions. ➃ The UCIe manageability architecture provides a standardized test and debugging infrastructure for UCIe-based SiPs. ➄ UCIe supports three packaging options: standard (2D), advanced (2.5D), and UCIe-3D, catering to a range of performance and cost requirements.
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