➀ Intel and Cadence collaborate to advance the UCIe standard, focusing on multi-die design and interoperability. ➁ The collaboration aims to address technical challenges in UCIe compliance and pre-silicon interoperability. ➂ The white paper details the strategies and technical advancements in building an open chiplet ecosystem.

➀ The automotive industry's demand for high-capacity, high-speed storage solutions has led to the adoption of SPI Octal DDR NAND Flash, which presents unique verification challenges. ➁ Traditional verification models for NOR Flash are inadequate for simulating the complex architecture of Octal SPI NAND devices. ➂ Cadence, in collaboration with Winbond, has developed an enhanced SPI NAND Flash Memory Model to address these challenges, ensuring reliable performance in automotive applications.

1. PAM4 SerDes technology significantly enhances data throughput and power efficiency for AI and data center applications; 2. The technology supports various reach requirements, from long to short, ensuring reliable and high-speed data transmission; 3. Cadence's advanced SerDes solutions and involvement in the Ultra Ethernet Consortium highlight ongoing innovations in Ethernet technology.

1. Cadence introduces the Janus NoC IP to enhance its system IP portfolio, addressing complex interconnect challenges in SoCs. 2. The Janus NoC provides scalable architecture, efficient communication, and supports dynamic configurations for multi-chip and chiplet designs. 3. It leverages Cadence's extensive software and hardware offerings, ensuring high performance, power efficiency, and area optimization.

1. Timing closure is critical for final chip design sign-off, especially with increasing interconnect resistance and capacitance parasitics. 2. Analog design lacks automation and heavily relies on handcrafted layouts and hand-estimated parasitics, leading to more post-layout issues. 3. The Cadence Quantus Insight Solution aims to accelerate expert designer insight and suggested fixes before long-cycle layout changes and re-simulation.

1. Cadence has expanded its system IP portfolio with the introduction of the Cadence Janus Network-on-Chip (NoC). 2. The new NoC aims to optimize electronic system connectivity. 3. This expansion is expected to improve performance, power, and area (PPA) faster and with lower risk.

1. Cadence has announced a proprietary optical connectivity solution for PCIe 7.0. 2. The new solution promises data transfer speeds of up to 128 GT/s. 3. This development marks a significant advancement in high-speed data communication technologies.

At CadenceLIVE 2024 Anirudh Devgan (President and CEO of Cadence) hosted two fireside chats, one with Jensen Huang (President and CEO of NVIDIA) and one with Cristiano Amon (President and CEO of Qualcomm). As you would expect both discussions were engaging and enlightening. What follows are my takeaways from those chats. Anirudh … Read More The post Anirudh Fireside Chats with Jensen and Cristiano appeared first on SemiWiki.

The great things about CEO keynotes, at least from larger companies, is that you not only learn about recent advances but you also get a sense of the underlying algorithm for growth. Particularly reinforced when followed by discussions with high profile partner CEOs on their directions and areas of common interest. I saw this recently… Read More The post Anirudh Keynote at CadenceLIVE 2024. Big Advances, Big Goals appeared first on SemiWiki.