09/11/2024, 08:31 PM UTC
慧荣科技选用Arteris Interconnect IP进行高性能SoC设计Arteris Interconnect IP Selected by VeriSilicon for High-Performance SoC Design
➀ 慧荣科技选择Arteris FlexNoC 5互连IP进行高性能SoC设计；➁ 该互连IP提供增强的成本和设计效率；➂ 该IP具备物理感知能力，且具有可扩展性。➀ VeriSilicon selects Arteris FlexNoC 5 interconnect IP for high-performance SoC design; ➁ The interconnect IP provides enhanced cost and design efficiency; ➂ The IP is physically aware and offers scalability.
---
本文由大语言模型（LLM）生成，旨在为读者提供半导体新闻内容的知识扩展（Beta）。
