10/14/2024, 08:31 AM UTC
台积电要用5nm先进封装HBM4内存芯片？TSMC to Utilize 5nm Advanced Packaging HBM4 Memory Chips?
<p>➀ 台积电的HBM4内存推出将带来多项重大变革，其中最引人注目的是内存接口从1024位扩展到2048位；</p><p>➁ 在2024年欧洲技术研讨会上，台积电透露了其为HBM4制造的base die的一些细节，这些芯片将采用逻辑工艺制造，台积电计划利用其N12和N5工艺的改进版本生产这些芯片；</p><p>➂ 对于HBM4的首批产品封装，台积电将采用N12FFC+和N5两种不同的制造工艺；</p><p>➃ 台积电正与美光、三星和SK海力士等主要HBM内存供应商合作，利用先进的工艺节点推进HBM4内存技术的全面整合；</p><p>➄ 台积电的N12FFC+工艺非常适合实现HBM4的性能，使内存制造商能够构建12-Hi（48GB）和16-Hi（64GB）堆栈，每个堆栈的带宽超过2TB/秒；</p><p>➅ 台积电的N5工艺将集成更多逻辑功能，减少功耗并提供更高的性能，实现非常小的互连间距，允许HBM4直接3D堆叠在逻辑芯片上从而大幅提升内存性能。</p><p>➀ TSMC's HBM4 memory launch brings significant changes, with the most noticeable being the expansion of memory interfaces from 1024 to 2048 bits;</p><p>➁ TSMC revealed details about base die for HBM4 manufacturing using improved versions of its N12 and N5 processes at the 2024 European Technology Symposium;</p><p>➂ TSMC plans to adopt two different manufacturing processes, N12FFC+ and N5, for the first batch of HBM4 product packaging;</p><p>➃ TSMC is working with major HBM memory suppliers like Micron, Samsung, and SK Hynix to integrate HBM4 memory technology using advanced process nodes;</p><p>➄ TSMC's N12FFC+ process is suitable for achieving HBM4 performance, allowing memory manufacturers to build 12-Hi (48GB) and 16-Hi (64GB) stacks with over 2TB/s bandwidth;</p><p>➅ TSMC's N5 process will integrate more logic functions, reduce power consumption, and provide higher performance with very small interconnect spacing, enabling HBM4 direct 3D stacking on logic chips.</p>
---
本文由大语言模型（LLM）生成，旨在为读者提供半导体新闻内容的知识扩展（Beta）。
