10/30/2024, 03:21 PM UTC
新型混合存储器旨在减少人工智能的能源使用Next-Gen Hybrid Memory Aims to Reduce AI Energy Consumption
<p>➀ 斯坦福大学正在研究一种结合DRAM的密度和SRAM的速度的混合存储器，该项目得到CHIPS和科学法案的资助。</p><p>➁ 该研究是加州太平洋西北人工智能硬件中心的一个项目，该中心将从美国国防部获得1630万美元的资助。</p><p>➂ 该团队由H.S. Philip Wong领导，专注于为人工智能开发更节能的硬件，内存是实现这一目标的核心。</p><p>➃ 混合增益单元存储器结合了DRAM的小占位空间和几乎与SRAM一样快的速度。</p><p>➄ 增益单元类似于DRAM，但使用第二个晶体管而不是电容器来存储数据，数据以电荷的形式存储在晶体管的栅极上。</p><p>➅ 读取信号在增益单元中是无损的，读取晶体管在读取时为存储晶体管提供增益。</p><p>➆ Liu和Wong的混合增益单元存储器，结合了硅读取晶体管和氧化铟锡写入晶体管，克服了局限性，实现了超过5000秒 的数据保持时间。</p><p>➇ 这些混合存储单元可以集成到逻辑芯片上，可能改变计算机中内存的使用方式。</p><p>➀ Stanford University is researching a hybrid memory that combines the density of DRAM with the speed of SRAM, funded by CHIPS and Science Act.</p><p>➁ The research is part of the California Pacific Northwest AI Hardware Center project, which will receive $16.3 million from the US Department of Defense.</p><p>➂ The team, led by H.S. Philip Wong, focuses on developing more energy-efficient hardware for AI, with memory being the core.</p><p>➃ The hybrid gain cell memory combines the small footprint of DRAM with the almost as fast speed of SRAM.</p><p>➄ The gain cell, similar to DRAM, uses a second transistor instead of a capacitor to store data, with the data stored as charge on the gate of the transistor.</p><p>➅ Reading signals are无损 in the gain cell, and the reading transistor provides gain to the storage transistor during reading.</p><p>➆ Liu and Wong's mixed gain cell memory, combining silicon read transistors with indium tin oxide write transistors, overcomes limitations and achieves a data retention time of over 5000 seconds.</p><p>➇ These hybrid storage cells can be integrated into logic chips, potentially changing the way memory is used in computers.</p>
---
本文由大语言模型（LLM）生成，旨在为读者提供半导体新闻内容的知识扩展（Beta）。
