09/29/2024, 09:58 AM UTC
2nm来了，芯片连线怎么办？The Challenge of Chip Wiring with the Arrival of 2nm Technology
➀ 先进的逻辑芯片有高达20层的金属层来支撑两种类型的线；➁ 将电源线移至晶圆背面有望减少复杂性，增加晶体管空间；➂ 需要解决晶圆正面布线挑战，以将晶体管扩展到2nm以下；➃ 图形技术的进步允许打印更小的晶体管特性，但也要求更小的布线，导致电阻增加和信号延迟；➄ 材料和材料工程创新对于克服微型化和延长铜线寿命至关重要；➅ 行业正在寻求创新产品以将铜线扩展到2nm及以上。➀ Advanced logic chips have up to 20 metal layers to support two types of lines; ➁ The move of power lines to the back of the wafer is expected to reduce complexity and increase space for transistors; ➂ The challenges of wiring on the front side of the wafer need to be addressed to extend transistors to 2nm and below; ➃ The progression in graphic technology allows for smaller transistor characteristics but also requires smaller wiring, leading to increased resistance and signal delay; ➄ Innovations in materials and material engineering are crucial to overcome the challenges of miniaturization and extend the life of copper wiring; ➅ The industry is seeking innovative products to extend copper to 2nm and beyond.
---
本文由大语言模型（LLM）生成，旨在为读者提供半导体新闻内容的知识扩展（Beta）。
