华硕分享Core Ultra 9 285K官方晶圆照片 — 深入解析英特尔解耦方法
10/22/2024, 08:15 PM UTC
华硕分享Core Ultra 9 285K官方晶圆照片 — 深入解析英特尔解耦方法Asus shares official die shots of the Core Ultra 9 285K — In-depth annotations break down Intel's disaggregated approach
➀ 华硕分享Core Ultra 9 285K官方晶圆照片；➁ 英特尔Arrow Lake架构和3D Foveros封装技术；➂ 详细解析每个晶粒的布局和功能➀ Asus shares official die shots of the Core Ultra 9 285K; ➁ Intel's Arrow Lake architecture and 3D Foveros packaging technology; ➂ Detailed breakdown of each tile's layout and functionality
Asus has shared the first official die shots of Intel's Arrow Lake-based Core Ultra 9 285K, revealing insights into Intel's disaggregated approach.
Arrow Lake features a total of six tiles, including the Compute Tile, SoC Tile, IOE Tile, Graphics Tile, and two Filler Tiles. The Compute Tile, which hosts all the cores and cache, is the largest. The SoC Tile, built using TSMC's N6 node, houses the memory fabric and controllers, while the GPU Tile, based on the Alchemist architecture, features four Xe cores manufactured using TSMC's N5 node.
This modular design allows for flexibility in swapping tiles, but also introduces increased latency and packaging overhead. Intel's use of TSMC for most tiles, except for the Base Tile built on a 22nm process, highlights the collaboration between the two companies.
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