Technology giants TSMC, IBM, and Samsung are set to present their groundbreaking advancements in vertically-stacked complementary field-effect transistors (CFETs) at the International Electron Devices Meeting (IEDM) in December 2024. This gathering of industry leaders aims to showcase the latest research and development in semiconductor technology.

Among the innovations, TSMC's development of a monolithic CFET inverter on a 48nm gate pitch is particularly noteworthy. This design, which is equivalent to a 5nm process, features stacked n-type and p-type nanosheet transistors with backside contacts, achieving a voltage transfer up to 1.2V and a subthreshold slope between 74 and 76mV/V. Although not yet ready for commercial production, this marks a significant step forward for TSMC's CFET technology.

IBM Research and Samsung are also contributing to the discussion with a 'Monolithic Stacked FET' that employs a stepped channel design, which reduces stack height and addresses challenges associated with high aspect ratios. This research also includes isolation techniques and the use of dual work function metal.

IMEC, another key player in the field, is presenting a 'Double-Row CFET' designed for vertical and horizontal scaling, targeting the 7a-class fabrication process, which is several generations away.

While these advancements are years away from mass production, the IEDM conference serves as a testament to the ongoing progress in semiconductor technology and the pursuit of new, more efficient transistor designs.