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  • Predictive Load Handling: Solving a Quiet Bottleneck in Modern DSPs

    ➀ Memory stalls are a significant bottleneck in digital signal processors (DSPs) for embedded AI applications.

    ➁ Traditional DSP designs use non-cacheable memory regions, leading to pipeline stalls due to precise load latency requirements.

    ➂ Predictive Load Handling focuses on predicting memory access latency, rather than just prefetching data.

  • April 16

  • Executive Interview with Leo Linehan, President, Electronic Materials, Materion Corporation

    ➀ Materion is a global leader in advanced materials, particularly in the semiconductor industry.

    ➁ The Electronic Materials business provides specialty materials for thin film deposition and microelectronic packaging.

    ➂ Leo Linehan discusses the challenges of the current geopolitical situation and the company's strategies to mitigate issues.

  • April 15

  • CEO Interview with Ronald Glibbery of Peraso

    ➀ Peraso specializes in semiconductor solutions for the unlicensed 60 GHz spectrum, serving markets such as fixed wireless access, aerospace, and transportation communications.

    ➁ The company's mmWave technology provides reliable connectivity in dense urban environments through beamforming.

    ➂ Peraso is the only semiconductor supplier offering a complete 60GHz system solution.

  • SNUG 2025: A Watershed Moment for EDA – Part 1

    ➀ The SNUG 2025 conference highlighted the evolution of Synopsys and the EDA industry, emphasizing innovation and leadership.

    ➁ Sassine Ghazi, Synopsys’ CEO, emphasized the need to 're-engineer engineering' for AI-centric silicon design.

    ➂ Satya Nadella, CEO of Microsoft, discussed the accelerating complexity in hardware and software design, likening it to 'Moore’s Law on hyperdrive'.

  • April 11

  • Synopsys Webinar: The Importance of Security in Multi-Die Designs – Navigating the Complex Landscape

    ➀ The importance of security in electronic systems is highlighted by technological advancements and increasing regulatory demands.

    ➁ Multi-die designs introduce complexity and potential vulnerabilities, requiring robust security measures at every level.

    ➂ Regulations and standards are crucial in addressing security challenges, with the Cyber Resilience Act and ISO/SAE 21434 as notable examples.

  • April 10

  • Generative AI Comes to High-Level Design

    ➀ The EDA industry has evolved from transistor-level to high-level synthesis (HLS).

    ➁ Rise Design Automation introduces generative AI to automate RTL coding.

    ➂ The company's AI agents assist in synthesis, verification, and optimization.

  • April 9

  • Synopsys Executive Forum: Driving Silicon and Systems Engineering Innovation

    ➀ The Synopsys Executive Forum highlighted the challenges and opportunities in the semiconductor and electronics industry.

    ➁ AI is reshaping EDA workflows and semiconductor design, with AI-driven workflows offering substantial productivity gains.

    ➂ The forum discussed the impact of AI on various sectors, including healthcare, automotive, and education.

  • April 8

  • Stitched Multi-Patterning for Minimum Pitch Metal in DRAM Periphery

    ➀ In a DRAM chip, memory arrays are densely packed but lose regularity outside the array.

    ➁ Pitch uniformity can be achieved through layout splitting for double patterning with stitching.

    ➂ Triple patterning may be used for minimum pitches below 40 nm, and quadruple patterning may be replaced by triple patterning.

  • April 7

  • Even HBM Isn’t Fast Enough All the Time

    ➀ High Bandwidth Memory (HBM) is crucial for modern AI accelerators but is not always fast enough.

    ➁ Latency remains a significant issue, causing performance bottlenecks in AI processors.

    ➂ Latency-tolerant architectures are essential for maintaining performance in AI supercomputing.

  • April 1

  • A Synopsys Webinar Detailing IP Requirements for Advanced AI Chips

    ➀ The webinar discusses the impact of generative AI on technology evolution and the rise in compute power demand.

    ➁ It covers the trends in larger compute chips, multi-die systems, advanced packaging, and memory architectures.

    ➂ Key technologies like die-to-die communication, custom HBMs, and 3D stacking are explored in detail.

  • March 31

  • CEO Interview with Matthew Stephens of Impact Nano

    ➀ Matthew Stephens of Impact Nano has over 20 years of experience in advanced materials commercialization.

    ➁ Impact Nano is a tier 2 supplier specializing in advanced materials for semiconductor manufacturing.

    ➂ The company addresses challenges in materials innovation, scale-up, and manufacturing sustainability.

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